mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-24 16:32:20 +00:00
88cd7d0ea9
- Rename usages of CONFIG_SYS_DEF_EEPROM_ADDR to CONFIG_SYS_I2C_EEPROM_ADDR based on current usage. - Convert CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SYS_I2C_EEPROM_BUS, CONFIG_CONFIG_SYS_EEPROM_SIZE CONFIG_SYS_EEPROM_PAGE_WRITE_BITS and CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to Kconfig. We move these symbols around a bit and add appropriate dependencies to them. In some cases, we now add a correct default value as well. Signed-off-by: Tom Rini <trini@konsulko.com>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/* KMBEC FPGA (PRIO) */
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
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/*
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* High Level Configuration Options
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*/
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/*
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* System IO Setup
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*/
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#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
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/**
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* DDR RAM settings
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*/
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#define CONFIG_SYS_DDR_SDRAM_CFG (\
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SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#define CONFIG_SYS_DDR_CLK_CNTL (\
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL (\
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(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDRCDR (\
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DDRCDR_EN | \
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DDRCDR_Q_DRN)
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#define CONFIG_SYS_DDR_MODE 0x47860452
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#define CONFIG_SYS_DDR_MODE2 0x8080c000
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#define CONFIG_SYS_DDR_TIMING_0 (\
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(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 (\
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(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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/* EEprom support */
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/*
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* PAXE on the local bus CS3
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*/
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#define CONFIG_SYS_PAXE_BASE 0xA0000000
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#define CONFIG_SYS_PAXE_SIZE 256
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