mirror of
https://github.com/AsahiLinux/u-boot
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d13cd77068
This commit sychronizes the header file for FU740 PRCI clocks with the one from Linux 5.19. The constant values are the same, but all constant names are changed (most are just prefixed with FU740_). Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
733 lines
19 KiB
C
733 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2021 SiFive, Inc.
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* Wesley Terpstra
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* Paul Walmsley
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* Zong Li
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* Pragnesh Patel
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* The PRCI implements clock and reset control for the SiFive chip.
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* This driver assumes that it has sole control over all PRCI resources.
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*
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* This driver is based on the PRCI driver written by Wesley Terpstra:
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* https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <asm/arch/reset.h>
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#include <linux/delay.h>
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#include <linux/math64.h>
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#include <dt-bindings/clock/sifive-fu740-prci.h>
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#include "fu540-prci.h"
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#include "fu740-prci.h"
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/*
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* Private functions
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*/
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/**
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* __prci_readl() - read from a PRCI register
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* @pd: PRCI context
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* @offs: register offset to read from (in bytes, from PRCI base address)
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*
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* Read the register located at offset @offs from the base virtual
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* address of the PRCI register target described by @pd, and return
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* the value to the caller.
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*
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* Context: Any context.
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*
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* Return: the contents of the register described by @pd and @offs.
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*/
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static u32 __prci_readl(struct __prci_data *pd, u32 offs)
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{
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return readl(pd->va + offs);
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}
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static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
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{
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writel(v, pd->va + offs);
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}
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/* WRPLL-related private functions */
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/**
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* __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
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* @c: ptr to a struct wrpll_cfg record to write config into
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* @r: value read from the PRCI PLL configuration register
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*
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* Given a value @r read from an FU540 PRCI PLL configuration register,
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* split it into fields and populate it into the WRPLL configuration record
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* pointed to by @c.
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*
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* The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
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* have the same register layout.
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*
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* Context: Any context.
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*/
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static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
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{
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u32 v;
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v = r & PRCI_COREPLLCFG0_DIVR_MASK;
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v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
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c->divr = v;
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v = r & PRCI_COREPLLCFG0_DIVF_MASK;
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v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
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c->divf = v;
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v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
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v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
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c->divq = v;
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v = r & PRCI_COREPLLCFG0_RANGE_MASK;
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v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
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c->range = v;
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c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
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WRPLL_FLAGS_EXT_FEEDBACK_MASK);
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/* external feedback mode not supported */
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c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
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}
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/**
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* __prci_wrpll_pack() - pack PLL configuration parameters into a register value
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* @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
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*
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* Using a set of WRPLL configuration values pointed to by @c,
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* assemble a PRCI PLL configuration register value, and return it to
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* the caller.
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*
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* Context: Any context. Caller must ensure that the contents of the
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* record pointed to by @c do not change during the execution
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* of this function.
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*
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* Returns: a value suitable for writing into a PRCI PLL configuration
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* register
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*/
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static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
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{
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u32 r = 0;
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r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
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r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
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r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
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r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
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/* external feedback mode not supported */
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r |= PRCI_COREPLLCFG0_FSE_MASK;
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return r;
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}
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/**
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* __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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*
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* Read the current configuration of the PLL identified by @pwd from
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* the PRCI identified by @pd, and store it into the local configuration
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* cache in @pwd.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd)
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{
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__prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
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}
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/**
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* __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @c: WRPLL configuration record to write
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*
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* Write the WRPLL configuration described by @c into the WRPLL
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* configuration register identified by @pwd in the PRCI instance
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* described by @c. Make a cached copy of the WRPLL's current
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* configuration so it can be used by other code.
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*
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* Context: Any context. Caller must prevent the records pointed to by
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* @pd and @pwd from changing during execution.
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*/
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static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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struct wrpll_cfg *c)
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{
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__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
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memcpy(&pwd->c, c, sizeof(*c));
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}
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/**
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* __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
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* into the PRCI
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* @pd: PRCI context
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* @pwd: PRCI WRPLL metadata
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* @enable: Clock enable or disable value
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*/
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static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
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struct __prci_wrpll_data *pwd,
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u32 enable)
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{
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__prci_writel(enable, pwd->cfg1_offs, pd);
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}
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unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc,
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unsigned long parent_rate)
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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return wrpll_calc_output_rate(&pwd->c, parent_rate);
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}
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unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc,
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unsigned long rate,
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unsigned long *parent_rate)
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct wrpll_cfg c;
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memcpy(&c, &pwd->c, sizeof(c));
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wrpll_configure_for_rate(&c, rate, *parent_rate);
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return wrpll_calc_output_rate(&c, *parent_rate);
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}
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int sifive_prci_wrpll_set_rate(struct __prci_clock *pc,
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unsigned long rate,
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unsigned long parent_rate)
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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int r;
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r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
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if (r)
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return r;
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if (pwd->enable_bypass)
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pwd->enable_bypass(pd);
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__prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
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udelay(wrpll_calc_max_lock_us(&pwd->c));
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return 0;
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}
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int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable)
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{
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struct __prci_wrpll_data *pwd = pc->pwd;
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struct __prci_data *pd = pc->pd;
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if (enable) {
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__prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
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if (pwd->disable_bypass)
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pwd->disable_bypass(pd);
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if (pwd->release_reset)
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pwd->release_reset(pd);
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} else {
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u32 r;
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if (pwd->enable_bypass)
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pwd->enable_bypass(pd);
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r = __prci_readl(pd, pwd->cfg1_offs);
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r &= ~PRCI_COREPLLCFG1_CKE_MASK;
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__prci_wrpll_write_cfg1(pd, pwd, r);
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}
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return 0;
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}
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/* TLCLKSEL clock integration */
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unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc,
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unsigned long parent_rate)
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{
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struct __prci_data *pd = pc->pd;
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u32 v;
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u8 div;
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v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
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v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
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div = v ? 1 : 2;
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return div_u64(parent_rate, div);
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}
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/* HFPCLK clock integration */
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unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc,
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unsigned long parent_rate)
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{
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struct __prci_data *pd = pc->pd;
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u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);
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return div_u64(parent_rate, div + 2);
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}
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/**
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* sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
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* FINAL_COREPLL
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* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
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*
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* Switch the CORECLK mux to the final COREPLL output clock; return once
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* complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_CORECLKSEL_OFFSET register.
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*/
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void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
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r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
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__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
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* output DVFS_COREPLL
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* @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
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*
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* Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_COREPLLSEL_OFFSET register.
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*/
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void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
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r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;
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__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
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* output COREPLL
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* @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
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*
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* Switch the COREPLL mux to the COREPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_COREPLLSEL_OFFSET register.
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*/
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void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
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r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;
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__prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
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* output HFCLK
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* @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
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*
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* Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_HFPCLKPLLSEL_OFFSET register.
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*/
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void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
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r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
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__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
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}
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/**
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* sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
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* output HFPCLKPLL
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* @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
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*
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* Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
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*
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* Context: Any context. Caller must prevent concurrent changes to the
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* PRCI_HFPCLKPLLSEL_OFFSET register.
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*/
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void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
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{
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u32 r;
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
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r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
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__prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
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r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
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}
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static int __prci_consumer_reset(const char *rst_name, bool trigger)
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{
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struct udevice *dev;
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struct reset_ctl rst_sig;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_RESET,
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DM_DRIVER_GET(sifive_reset),
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&dev);
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if (ret) {
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dev_err(dev, "Reset driver not found: %d\n", ret);
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return ret;
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}
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ret = reset_get_by_name(dev, rst_name, &rst_sig);
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if (ret) {
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dev_err(dev, "failed to get %s reset\n", rst_name);
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return ret;
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}
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if (reset_valid(&rst_sig)) {
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if (trigger)
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ret = reset_deassert(&rst_sig);
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else
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ret = reset_assert(&rst_sig);
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if (ret) {
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dev_err(dev, "failed to trigger reset id = %ld\n",
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rst_sig.id);
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return ret;
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}
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}
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return ret;
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}
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/**
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* sifive_prci_ddr_release_reset() - Release DDR reset
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* @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
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*
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*/
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void sifive_prci_ddr_release_reset(struct __prci_data *pd)
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{
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/* Release DDR ctrl reset */
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__prci_consumer_reset("ddr_ctrl", true);
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/* HACK to get the '1 full controller clock cycle'. */
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asm volatile ("fence");
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/* Release DDR AXI reset */
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__prci_consumer_reset("ddr_axi", true);
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/* Release DDR AHB reset */
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__prci_consumer_reset("ddr_ahb", true);
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/* Release DDR PHY reset */
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__prci_consumer_reset("ddr_phy", true);
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/* HACK to get the '1 full controller clock cycle'. */
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asm volatile ("fence");
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/*
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* These take like 16 cycles to actually propagate. We can't go sending
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* stuff before they come out of reset. So wait.
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*/
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for (int i = 0; i < 256; i++)
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asm volatile ("nop");
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}
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/**
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* sifive_prci_ethernet_release_reset() - Release ethernet reset
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* @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
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*
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*/
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void sifive_prci_ethernet_release_reset(struct __prci_data *pd)
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{
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/* Release GEMGXL reset */
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__prci_consumer_reset("gemgxl_reset", true);
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/* Procmon => core clock */
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__prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
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pd);
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/* Release Chiplink reset */
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__prci_consumer_reset("cltx_reset", true);
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}
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/**
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* sifive_prci_cltx_release_reset() - Release cltx reset
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* @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
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*
|
|
*/
|
|
void sifive_prci_cltx_release_reset(struct __prci_data *pd)
|
|
{
|
|
/* Release CLTX reset */
|
|
__prci_consumer_reset("cltx_reset", true);
|
|
}
|
|
|
|
/* Core clock mux control */
|
|
|
|
/**
|
|
* sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
|
|
* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
|
|
*
|
|
* Switch the CORECLK mux to the HFCLK input source; return once complete.
|
|
*
|
|
* Context: Any context. Caller must prevent concurrent changes to the
|
|
* PRCI_CORECLKSEL_OFFSET register.
|
|
*/
|
|
void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)
|
|
{
|
|
u32 r;
|
|
|
|
r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
|
|
r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
|
|
__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
|
|
|
|
r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
|
|
}
|
|
|
|
/**
|
|
* sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
|
|
* @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
|
|
*
|
|
* Switch the CORECLK mux to the PLL output clock; return once complete.
|
|
*
|
|
* Context: Any context. Caller must prevent concurrent changes to the
|
|
* PRCI_CORECLKSEL_OFFSET register.
|
|
*/
|
|
void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)
|
|
{
|
|
u32 r;
|
|
|
|
r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
|
|
r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
|
|
__prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
|
|
|
|
r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
|
|
}
|
|
|
|
static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data)
|
|
{
|
|
ulong parent_rate;
|
|
ulong i;
|
|
struct __prci_clock *p;
|
|
|
|
if (strcmp(pc->parent_name, "corepll") == 0 ||
|
|
strcmp(pc->parent_name, "hfpclkpll") == 0) {
|
|
for (i = 0; i < data->num_clks; i++) {
|
|
if (strcmp(pc->parent_name, data->clks[i].name) == 0)
|
|
break;
|
|
}
|
|
|
|
if (i >= data->num_clks)
|
|
return -ENXIO;
|
|
|
|
p = &data->clks[i];
|
|
if (!p->pd || !p->ops->recalc_rate)
|
|
return -ENXIO;
|
|
|
|
return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data));
|
|
}
|
|
|
|
if (strcmp(pc->parent_name, "rtcclk") == 0)
|
|
parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
|
|
else
|
|
parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
|
|
|
|
return parent_rate;
|
|
}
|
|
|
|
static ulong sifive_prci_get_rate(struct clk *clk)
|
|
{
|
|
struct __prci_clock *pc;
|
|
struct prci_clk_desc *data =
|
|
(struct prci_clk_desc *)dev_get_driver_data(clk->dev);
|
|
|
|
if (data->num_clks <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &data->clks[clk->id];
|
|
if (!pc->pd || !pc->ops->recalc_rate)
|
|
return -ENXIO;
|
|
|
|
return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data));
|
|
}
|
|
|
|
static ulong sifive_prci_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
int err;
|
|
struct __prci_clock *pc;
|
|
struct prci_clk_desc *data =
|
|
(struct prci_clk_desc *)dev_get_driver_data(clk->dev);
|
|
|
|
if (data->num_clks <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &data->clks[clk->id];
|
|
if (!pc->pd || !pc->ops->set_rate)
|
|
return -ENXIO;
|
|
|
|
err = pc->ops->set_rate(pc, rate, sifive_prci_parent_rate(pc, data));
|
|
if (err)
|
|
return err;
|
|
|
|
return rate;
|
|
}
|
|
|
|
static int sifive_prci_enable(struct clk *clk)
|
|
{
|
|
struct __prci_clock *pc;
|
|
int ret = 0;
|
|
struct prci_clk_desc *data =
|
|
(struct prci_clk_desc *)dev_get_driver_data(clk->dev);
|
|
|
|
if (data->num_clks <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &data->clks[clk->id];
|
|
if (!pc->pd)
|
|
return -ENXIO;
|
|
|
|
if (pc->ops->enable_clk)
|
|
ret = pc->ops->enable_clk(pc, 1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sifive_prci_disable(struct clk *clk)
|
|
{
|
|
struct __prci_clock *pc;
|
|
int ret = 0;
|
|
struct prci_clk_desc *data =
|
|
(struct prci_clk_desc *)dev_get_driver_data(clk->dev);
|
|
|
|
if (data->num_clks <= clk->id)
|
|
return -ENXIO;
|
|
|
|
pc = &data->clks[clk->id];
|
|
if (!pc->pd)
|
|
return -ENXIO;
|
|
|
|
if (pc->ops->enable_clk)
|
|
ret = pc->ops->enable_clk(pc, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int sifive_prci_probe(struct udevice *dev)
|
|
{
|
|
int i, err;
|
|
struct __prci_clock *pc;
|
|
struct __prci_data *pd = dev_get_priv(dev);
|
|
|
|
struct prci_clk_desc *data =
|
|
(struct prci_clk_desc *)dev_get_driver_data(dev);
|
|
|
|
pd->va = dev_read_addr_ptr(dev);
|
|
if (!pd->va)
|
|
return -EINVAL;
|
|
|
|
err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
|
|
if (err)
|
|
return err;
|
|
|
|
err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
|
|
if (err)
|
|
return err;
|
|
|
|
for (i = 0; i < data->num_clks; ++i) {
|
|
pc = &data->clks[i];
|
|
pc->pd = pd;
|
|
if (pc->pwd)
|
|
__prci_wrpll_read_cfg0(pd, pc->pwd);
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
|
|
if (device_is_compatible(dev, "sifive,fu740-c000-prci")) {
|
|
u32 prci_pll_reg;
|
|
unsigned long parent_rate;
|
|
|
|
prci_pll_reg = readl(pd->va + PRCI_PRCIPLL_OFFSET);
|
|
|
|
if (prci_pll_reg & PRCI_PRCIPLL_HFPCLKPLL) {
|
|
/*
|
|
* Only initialize the HFPCLK PLL. In this
|
|
* case the design uses hfpclk to drive
|
|
* Chiplink
|
|
*/
|
|
pc = &data->clks[FU740_PRCI_CLK_HFPCLKPLL];
|
|
parent_rate = sifive_prci_parent_rate(pc, data);
|
|
sifive_prci_wrpll_set_rate(pc, 260000000,
|
|
parent_rate);
|
|
pc->ops->enable_clk(pc, 1);
|
|
} else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
|
|
/* CLTX pll init */
|
|
pc = &data->clks[FU740_PRCI_CLK_CLTXPLL];
|
|
parent_rate = sifive_prci_parent_rate(pc, data);
|
|
sifive_prci_wrpll_set_rate(pc, 260000000,
|
|
parent_rate);
|
|
pc->ops->enable_clk(pc, 1);
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops sifive_prci_ops = {
|
|
.set_rate = sifive_prci_set_rate,
|
|
.get_rate = sifive_prci_get_rate,
|
|
.enable = sifive_prci_enable,
|
|
.disable = sifive_prci_disable,
|
|
};
|
|
|
|
static int sifive_clk_bind(struct udevice *dev)
|
|
{
|
|
return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
|
|
}
|
|
|
|
static const struct udevice_id sifive_prci_ids[] = {
|
|
{ .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 },
|
|
{ .compatible = "sifive,fu740-c000-prci", .data = (ulong)&prci_clk_fu740 },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(sifive_prci) = {
|
|
.name = "sifive-prci",
|
|
.id = UCLASS_CLK,
|
|
.of_match = sifive_prci_ids,
|
|
.probe = sifive_prci_probe,
|
|
.ops = &sifive_prci_ops,
|
|
.priv_auto = sizeof(struct __prci_data),
|
|
.bind = sifive_clk_bind,
|
|
};
|