mirror of
https://github.com/AsahiLinux/u-boot
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
364 lines
8.7 KiB
C
364 lines
8.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/lists.h>
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#include <dm/util.h>
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#include <linux/bitops.h>
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#include <asm/global_data.h>
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#include <asm/arch/clock_manager.h>
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enum socfpga_a10_clk_type {
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SOCFPGA_A10_CLK_MAIN_PLL,
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SOCFPGA_A10_CLK_PER_PLL,
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SOCFPGA_A10_CLK_PERIP_CLK,
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SOCFPGA_A10_CLK_GATE_CLK,
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SOCFPGA_A10_CLK_UNKNOWN_CLK,
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};
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struct socfpga_a10_clk_plat {
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enum socfpga_a10_clk_type type;
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struct clk_bulk clks;
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u32 regs;
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/* Fixed divider */
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u16 fix_div;
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/* Control register */
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u16 ctl_reg;
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/* Divider register */
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u16 div_reg;
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u8 div_len;
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u8 div_off;
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/* Clock gating register */
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u16 gate_reg;
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u8 gate_bit;
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};
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static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
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{
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struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
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u32 reg, maxval;
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if (plat->clks.count == 0)
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return 0;
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if (plat->clks.count == 1) {
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*upclk = &plat->clks.clks[0];
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return 0;
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}
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if (!plat->ctl_reg) {
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dev_err(clk->dev, "Invalid control register\n");
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return -EINVAL;
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}
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reg = readl(plat->regs + plat->ctl_reg);
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/* Assume PLLs are ON for now */
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if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {
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reg = (reg >> 8) & 0x3;
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maxval = 2;
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} else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {
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reg = (reg >> 8) & 0x3;
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maxval = 3;
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} else {
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reg = (reg >> 16) & 0x7;
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maxval = 4;
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}
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if (reg > maxval) {
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dev_err(clk->dev, "Invalid clock source\n");
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return -EINVAL;
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}
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*upclk = &plat->clks.clks[reg];
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return 0;
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}
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static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
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{
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struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
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struct clk *upclk = NULL;
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int ret;
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if (!enable && plat->gate_reg)
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clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
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ret = socfpga_a10_clk_get_upstream(clk, &upclk);
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if (ret)
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return ret;
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if (upclk) {
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if (enable)
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clk_enable(upclk);
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else
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clk_disable(upclk);
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}
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if (enable && plat->gate_reg)
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setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
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return 0;
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}
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static int socfpga_a10_clk_enable(struct clk *clk)
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{
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return socfpga_a10_clk_endisable(clk, true);
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}
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static int socfpga_a10_clk_disable(struct clk *clk)
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{
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return socfpga_a10_clk_endisable(clk, false);
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}
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static ulong socfpga_a10_clk_get_rate(struct clk *clk)
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{
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struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
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struct clk *upclk = NULL;
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ulong rate = 0, reg, numer, denom;
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int ret;
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ret = socfpga_a10_clk_get_upstream(clk, &upclk);
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if (ret || !upclk)
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return 0;
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rate = clk_get_rate(upclk);
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if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {
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reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */
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numer = reg & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
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denom = (reg >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
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CLKMGR_MAINPLL_VCO1_DENOM_MSK;
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rate /= denom + 1;
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rate *= numer + 1;
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} else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {
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reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */
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numer = reg & CLKMGR_PERPLL_VCO1_NUMER_MSK;
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denom = (reg >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
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CLKMGR_PERPLL_VCO1_DENOM_MSK;
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rate /= denom + 1;
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rate *= numer + 1;
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} else {
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rate /= plat->fix_div;
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if (plat->fix_div == 1 && plat->ctl_reg) {
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reg = readl(plat->regs + plat->ctl_reg);
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reg &= 0x7ff;
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rate /= reg + 1;
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}
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if (plat->div_reg) {
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reg = readl(plat->regs + plat->div_reg);
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reg >>= plat->div_off;
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reg &= (1 << plat->div_len) - 1;
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if (plat->type == SOCFPGA_A10_CLK_PERIP_CLK)
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rate /= reg + 1;
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if (plat->type == SOCFPGA_A10_CLK_GATE_CLK)
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rate /= 1 << reg;
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}
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}
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return rate;
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}
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static struct clk_ops socfpga_a10_clk_ops = {
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.enable = socfpga_a10_clk_enable,
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.disable = socfpga_a10_clk_disable,
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.get_rate = socfpga_a10_clk_get_rate,
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};
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/*
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* This workaround tries to fix the massively broken generated "handoff" DT,
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* which contains duplicate clock nodes without any connection to the clock
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* manager DT node. Yet, those "handoff" DT nodes contain configuration of
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* the fixed input clock of the Arria10 which are missing from the base DT
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* for Arria10.
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*
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* This workaround sets up upstream clock for the fixed input clocks of the
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* A10 described in the base DT such that they map to the fixed clock from
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* the "handoff" DT. This does not fully match how the clock look on the
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* A10, but it is the least intrusive way to fix this mess.
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*/
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static void socfpga_a10_handoff_workaround(struct udevice *dev)
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{
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struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
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const void *fdt = gd->fdt_blob;
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struct clk_bulk *bulk = &plat->clks;
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int i, ret, offset = dev_of_offset(dev);
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static const char * const socfpga_a10_fixedclk_map[] = {
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"osc1", "altera_arria10_hps_eosc1",
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"cb_intosc_ls_clk", "altera_arria10_hps_cb_intosc_ls",
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"f2s_free_clk", "altera_arria10_hps_f2h_free",
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};
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if (fdt_node_check_compatible(fdt, offset, "fixed-clock"))
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return;
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for (i = 0; i < ARRAY_SIZE(socfpga_a10_fixedclk_map); i += 2)
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if (!strcmp(dev->name, socfpga_a10_fixedclk_map[i]))
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break;
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if (i == ARRAY_SIZE(socfpga_a10_fixedclk_map))
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return;
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ret = uclass_get_device_by_name(UCLASS_CLK,
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socfpga_a10_fixedclk_map[i + 1], &dev);
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if (ret)
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return;
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bulk->count = 1;
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bulk->clks = devm_kcalloc(dev, bulk->count,
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sizeof(struct clk), GFP_KERNEL);
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if (!bulk->clks)
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return;
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ret = clk_request(dev, &bulk->clks[0]);
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if (ret)
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free(bulk->clks);
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}
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static int socfpga_a10_clk_bind(struct udevice *dev)
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{
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const void *fdt = gd->fdt_blob;
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int offset = dev_of_offset(dev);
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bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
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const char *name;
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int ret;
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for (offset = fdt_first_subnode(fdt, offset);
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offset > 0;
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offset = fdt_next_subnode(fdt, offset)) {
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name = fdt_get_name(fdt, offset, NULL);
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if (!name)
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return -EINVAL;
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if (!strcmp(name, "clocks")) {
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offset = fdt_first_subnode(fdt, offset);
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name = fdt_get_name(fdt, offset, NULL);
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if (!name)
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return -EINVAL;
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}
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/* Filter out supported sub-clock */
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if (fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-pll-clock") &&
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fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-perip-clk") &&
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fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-gate-clk") &&
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fdt_node_check_compatible(fdt, offset, "fixed-clock"))
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continue;
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if (pre_reloc_only &&
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!ofnode_pre_reloc(offset_to_ofnode(offset)))
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continue;
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ret = device_bind_driver_to_node(dev, "clk-a10", name,
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offset_to_ofnode(offset),
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NULL);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int socfpga_a10_clk_probe(struct udevice *dev)
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{
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struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
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struct socfpga_a10_clk_plat *pplat;
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struct udevice *pdev;
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const void *fdt = gd->fdt_blob;
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int offset = dev_of_offset(dev);
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clk_get_bulk(dev, &plat->clks);
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socfpga_a10_handoff_workaround(dev);
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if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
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plat->regs = dev_read_addr(dev);
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} else {
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pdev = dev_get_parent(dev);
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if (!pdev)
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return -ENODEV;
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pplat = dev_get_plat(pdev);
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if (!pplat)
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return -EINVAL;
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plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
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plat->regs = pplat->regs;
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}
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if (!fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-pll-clock")) {
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/* Main PLL has 3 upstream clock */
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if (plat->clks.count == 3)
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plat->type = SOCFPGA_A10_CLK_MAIN_PLL;
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else
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plat->type = SOCFPGA_A10_CLK_PER_PLL;
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} else if (!fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-perip-clk")) {
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plat->type = SOCFPGA_A10_CLK_PERIP_CLK;
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} else if (!fdt_node_check_compatible(fdt, offset,
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"altr,socfpga-a10-gate-clk")) {
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plat->type = SOCFPGA_A10_CLK_GATE_CLK;
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} else {
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plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
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}
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return 0;
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}
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static int socfpga_a10_of_to_plat(struct udevice *dev)
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{
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struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
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unsigned int divreg[3], gatereg[2];
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int ret;
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plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
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plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1);
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ret = dev_read_u32_array(dev, "div-reg", divreg, ARRAY_SIZE(divreg));
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if (!ret) {
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plat->div_reg = divreg[0];
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plat->div_len = divreg[2];
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plat->div_off = divreg[1];
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}
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ret = dev_read_u32_array(dev, "clk-gate", gatereg, ARRAY_SIZE(gatereg));
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if (!ret) {
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plat->gate_reg = gatereg[0];
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plat->gate_bit = gatereg[1];
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}
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return 0;
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}
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static const struct udevice_id socfpga_a10_clk_match[] = {
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{ .compatible = "altr,clk-mgr" },
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{}
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};
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U_BOOT_DRIVER(socfpga_a10_clk) = {
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.name = "clk-a10",
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.id = UCLASS_CLK,
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.of_match = socfpga_a10_clk_match,
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.ops = &socfpga_a10_clk_ops,
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.bind = socfpga_a10_clk_bind,
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.probe = socfpga_a10_clk_probe,
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.of_to_plat = socfpga_a10_of_to_plat,
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.plat_auto = sizeof(struct socfpga_a10_clk_plat),
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};
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