u-boot/arch/xtensa/include/asm/system.h
Chris Zankel c978b52410 xtensa: add support for the xtensa processor architecture [2/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Tensilica, inc.

This is the second part of the basic architecture port, adding the
'arch/xtensa' directory and a readme file.

Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-15 18:46:38 -04:00

27 lines
602 B
C

/*
* Copyright (C) 2016 Cadence Design Systems Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _XTENSA_SYSTEM_H
#define _XTENSA_SYSTEM_H
#include <asm/arch/core.h>
#if XCHAL_HAVE_INTERRUPTS
#define local_irq_save(flags) \
__asm__ __volatile__ ("rsil %0, %1" \
: "=a"(flags) \
: "I"(XCHAL_EXCM_LEVEL) \
: "memory")
#define local_irq_restore(flags) \
__asm__ __volatile__ ("wsr %0, ps\n\t" \
"rsync" \
:: "a"(flags) : "memory")
#else
#define local_irq_save(flags) ((void)(flags))
#define local_irq_restore(flags) ((void)(flags))
#endif
#endif