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c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
152 lines
2.7 KiB
C
152 lines
2.7 KiB
C
/*
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* Copyright (C) 2005 - 2013 Tensilica Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_ASMMACRO_H
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#define _XTENSA_ASMMACRO_H
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#include <asm/arch/core.h>
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/*
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* Function entry and return macros for supported ABIs.
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*/
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#if defined(__XTENSA_WINDOWED_ABI__)
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#define abi_entry entry sp, 16
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#define abi_ret retw
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#elif defined(__XTENSA_CALL0_ABI__)
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#define abi_entry
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#define abi_ret ret
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#else
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#error Unsupported Xtensa ABI
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#endif
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/*
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* Some little helpers for loops. Use zero-overhead-loops
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* where applicable and if supported by the processor.
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*
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* __loopi ar, at, size, inc
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* ar register initialized with the start address
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* at scratch register used by macro
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* size size immediate value
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* inc increment
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*
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* __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
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* ar register initialized with the start address
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* as register initialized with the size
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* at scratch register use by macro
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* inc_log2 increment [in log2]
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* mask_log2 mask [in log2]
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* cond true condition (used in loop'cond')
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* ncond false condition (used in b'ncond')
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*
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* __loop as
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* restart loop. 'as' register must not have been modified!
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*
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* __endla ar, as, incr
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* ar start address (modified)
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* as scratch register used by __loops/__loopi macros or
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* end address used by __loopt macro
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* inc increment
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*/
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#if XCHAL_HAVE_LOOPS
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.macro __loopi ar, at, size, incr
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movi \at, ((\size + \incr - 1) / (\incr))
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loop \at, 99f
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.endm
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.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
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.ifgt \incr_log2 - 1
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addi \at, \as, (1 << \incr_log2) - 1
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.ifnc \mask_log2,
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extui \at, \at, \incr_log2, \mask_log2
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.else
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srli \at, \at, \incr_log2
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.endif
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.endif
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loop\cond \at, 99f
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.endm
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.macro __loopt ar, as, at, incr_log2
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sub \at, \as, \ar
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.ifgt \incr_log2 - 1
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addi \at, \at, (1 << \incr_log2) - 1
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srli \at, \at, \incr_log2
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.endif
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loop \at, 99f
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.endm
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.macro __loop as
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loop \as, 99f
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.endm
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.macro __endl ar, as
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99:
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.endm
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#else
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.macro __loopi ar, at, size, incr
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movi \at, ((\size + \incr - 1) / (\incr))
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addi \at, \ar, \size
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98:
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.endm
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.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
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.ifnc \mask_log2,
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extui \at, \as, \incr_log2, \mask_log2
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.else
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.ifnc \ncond,
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srli \at, \as, \incr_log2
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.endif
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.endif
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.ifnc \ncond,
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b\ncond \at, 99f
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.endif
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.ifnc \mask_log2,
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slli \at, \at, \incr_log2
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add \at, \ar, \at
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.else
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add \at, \ar, \as
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.endif
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98:
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.endm
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.macro __loopt ar, as, at, incr_log2
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98:
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.endm
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.macro __loop as
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98:
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.endm
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.macro __endl ar, as
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bltu \ar, \as, 98b
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99:
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.endm
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#endif
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.macro __endla ar, as, incr
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addi \ar, \ar, \incr
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__endl \ar \as
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.endm
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#endif /* _XTENSA_ASMMACRO_H */
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