Tien Fong Chee 59d4230429 ddr: altera: Add SDRAM driver for Intel N5X device ... The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>		2021-08-25 13:47:05 +08:00
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Kconfig	arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64	2021-03-08 10:59:10 +08:00
Makefile	ddr: altera: Add SDRAM driver for Intel N5X device	2021-08-25 13:47:05 +08:00
sdram_agilex.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
sdram_arria10.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
sdram_gen5.c	dm: Use access methods for dev/uclass private data	2021-01-05 12:24:40 -07:00
sdram_n5x.c	ddr: altera: Add SDRAM driver for Intel N5X device	2021-08-25 13:47:05 +08:00
sdram_s10.c	common: Drop asm/global_data.h from common header	2021-02-02 15:33:42 -05:00
sdram_s10.h	ddr: altera: Restructure Stratix 10 SDRAM driver	2020-01-07 14:38:33 +01:00
sdram_soc64.c	ddr: altera: Add SDRAM driver for Intel N5X device	2021-08-25 13:47:05 +08:00
sdram_soc64.h	ddr: altera: Add SDRAM driver for Intel N5X device	2021-08-25 13:47:05 +08:00
sequencer.c	dm: ddr: socfpga: don't assign values that are not used	2021-02-24 16:51:49 -05:00
sequencer.h	ddr: altera: Add DDR2 support to Gen5 driver	2020-02-05 03:01:57 +01:00