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u-boot/arch/arm/mach-socfpga
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Tien Fong Chee 59d4230429 ddr: altera: Add SDRAM driver for Intel N5X device 
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.

Configuration settings of controller, PHY and  memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.

Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.

The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25 13:47:05 +08:00
..
include/mach ddr: altera: Add SDRAM driver for Intel N5X device 2021-08-25 13:47:05 +08:00
board.c arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function 2021-08-24 14:29:50 +08:00
clock_manager.c arm: socfpga: Changed to store QSPI reference clock in kHz 2021-04-08 17:29:12 +08:00
clock_manager_agilex.c arm: socfpga: Move Stratix10 and Agilex clock manager common code 2021-04-08 17:29:12 +08:00
clock_manager_arria10.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
clock_manager_gen5.c arm: socfpga: Convert clock manager from struct to defines 2020-01-07 14:38:33 +01:00
clock_manager_n5x.c arm: socfpga: Add clock manager for Intel N5X device 2021-08-25 13:32:50 +08:00
clock_manager_s10.c arm: socfpga: Move Stratix10 and Agilex clock manager common code 2021-04-08 17:29:12 +08:00
firewall.c arm: socfpga: Move Stratix10 and Agilex system manager common code 2020-01-07 14:38:33 +01:00
fpga_manager.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
freeze_controller.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
Kconfig arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) 2021-03-08 10:59:10 +08:00
lowlevel_init_soc64.S arm: socfpga: soc64: Override 'lowlevel_init' to support ATF 2021-01-15 17:48:35 +08:00
mailbox_s10.c arm: socfpga: Changed to store QSPI reference clock in kHz 2021-04-08 17:29:12 +08:00
Makefile arm: socfpga: Changed misc_s10.c to misc_soc64.c 2021-08-25 13:37:01 +08:00
misc.c arm: socfpga: Get clock manager base address for Intel N5X device 2021-08-25 12:54:37 +08:00
misc_arria10.c common: Drop init.h from common header 2020-05-18 17:33:33 -04:00
misc_gen5.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
misc_soc64.c arm: socfpga: Changed misc_s10.c to misc_soc64.c 2021-08-25 13:37:01 +08:00
mmu-arm64_s10.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
pinmux_arria10.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
qts-filter-a10.sh arm: socfpga: arria10: Add qts-filter for Arria10 socfpga 2020-10-09 17:53:14 +08:00
qts-filter.sh ddr: altera: Add DDR2 support to Gen5 driver 2020-02-05 03:01:57 +01:00
reset_manager_arria10.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
reset_manager_gen5.c common: Drop linux/bitops.h from common header 2020-05-18 21:19:23 -04:00
reset_manager_s10.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
scan_manager.c common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
secure_reg_helper.c arm: socfpga: Add secure register access helper functions for SoC 64bits 2021-01-15 17:48:36 +08:00
secure_vab.c arm: socfpga: soc64: Support Vendor Authorized Boot (VAB) 2021-03-08 10:59:10 +08:00
smc_api.c arm: socfpga: smc: Add function to get usercode 2021-04-08 17:29:13 +08:00
spl_a10.c treewide: Convert macro and uses of __section(foo) to __section("foo") 2021-05-24 14:21:30 -04:00
spl_agilex.c arm: socfpga: Move Stratix10 and Agilex SPL common code 2021-04-08 17:29:11 +08:00
spl_gen5.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
spl_s10.c arm: socfpga: Move Stratix10 and Agilex SPL common code 2021-04-08 17:29:11 +08:00
spl_soc64.c arm: socfpga: Move Stratix10 and Agilex SPL common code 2021-04-08 17:29:11 +08:00
system_manager_gen5.c arm: socfpga: Convert system manager from struct to defines 2020-01-07 14:38:33 +01:00
system_manager_soc64.c arm: socfpga: Add handoff data support for Intel N5X device 2021-08-24 17:13:35 +08:00
timer.c common: Drop init.h from common header 2020-05-18 17:33:33 -04:00
timer_s10.c arm: socfpga: soc64: Initialize timer in SPL only 2020-10-09 17:53:11 +08:00
vab.c global: Convert simple_strtoul() with hex to hextoul() 2021-08-02 13:32:14 -04:00
wrap_handoff_soc64.c arm: socfpga: Add handoff data support for Intel N5X device 2021-08-24 17:13:35 +08:00
wrap_iocsr_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pinmux_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pll_config.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
wrap_pll_config_soc64.c arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c 2021-04-08 17:29:12 +08:00
wrap_sdram_config.c ddr: altera: Add DDR2 support to Gen5 driver 2020-02-05 03:01:57 +01:00