mirror of
https://github.com/AsahiLinux/u-boot
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a12a73b664
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
154 lines
2.9 KiB
C
154 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Sumit Garg <sumit.garg@linaro.org>
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*
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* Based on Linux driver
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*/
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <linux/bitops.h>
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#include <asm/io.h>
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#include <reset.h>
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#include <clk.h>
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#include <linux/delay.h>
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#define PHY_CTRL0 0x6C
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#define PHY_CTRL1 0x70
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#define PHY_CTRL2 0x74
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#define PHY_CTRL4 0x7C
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/* PHY_CTRL bits */
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#define REF_PHY_EN BIT(0)
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#define LANE0_PWR_ON BIT(2)
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#define SWI_PCS_CLK_SEL BIT(4)
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#define TST_PWR_DOWN BIT(4)
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#define PHY_RESET BIT(7)
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struct ssphy_priv {
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void __iomem *base;
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struct clk_bulk clks;
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struct reset_ctl com_rst;
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struct reset_ctl phy_rst;
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};
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static inline void ssphy_updatel(void __iomem *addr, u32 mask, u32 val)
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{
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writel((readl(addr) & ~mask) | val, addr);
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}
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static int ssphy_do_reset(struct ssphy_priv *priv)
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{
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int ret;
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ret = reset_assert(&priv->com_rst);
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if (ret)
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return ret;
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ret = reset_assert(&priv->phy_rst);
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if (ret)
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return ret;
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udelay(10);
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ret = reset_deassert(&priv->com_rst);
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if (ret)
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return ret;
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ret = reset_deassert(&priv->phy_rst);
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if (ret)
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return ret;
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return 0;
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}
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static int ssphy_power_on(struct phy *phy)
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{
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struct ssphy_priv *priv = dev_get_priv(phy->dev);
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int ret;
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ret = ssphy_do_reset(priv);
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if (ret)
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return ret;
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writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0);
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ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON);
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ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN);
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ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0);
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return 0;
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}
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static int ssphy_power_off(struct phy *phy)
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{
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struct ssphy_priv *priv = dev_get_priv(phy->dev);
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ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0);
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ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0);
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ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
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return 0;
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}
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static int ssphy_clk_init(struct udevice *dev, struct ssphy_priv *priv)
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{
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int ret;
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ret = clk_get_bulk(dev, &priv->clks);
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if (ret == -ENOSYS || ret == -ENOENT)
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return 0;
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if (ret)
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return ret;
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ret = clk_enable_bulk(&priv->clks);
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if (ret) {
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clk_release_bulk(&priv->clks);
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return ret;
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}
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return 0;
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}
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static int ssphy_probe(struct udevice *dev)
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{
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struct ssphy_priv *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -EINVAL;
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ret = ssphy_clk_init(dev, priv);
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if (ret)
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return ret;
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ret = reset_get_by_name(dev, "com", &priv->com_rst);
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if (ret)
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return ret;
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ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
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if (ret)
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return ret;
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return 0;
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}
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static struct phy_ops ssphy_ops = {
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.power_on = ssphy_power_on,
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.power_off = ssphy_power_off,
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};
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static const struct udevice_id ssphy_ids[] = {
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{ .compatible = "qcom,usb-ss-28nm-phy" },
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{ }
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};
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U_BOOT_DRIVER(qcom_usb_ss) = {
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.name = "qcom-usb-ss",
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.id = UCLASS_PHY,
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.of_match = ssphy_ids,
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.ops = &ssphy_ops,
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.probe = ssphy_probe,
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.priv_auto = sizeof(struct ssphy_priv),
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};
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