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73223f0e1b
There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
27 lines
838 B
Text
27 lines
838 B
Text
CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN7I=y
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CONFIG_DRAM_CLK=408
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CONFIG_MMC0_CD_PIN="PH1"
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CONFIG_MMC1_CD_PIN="PH2"
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CONFIG_MMC1_PINS="PH"
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CONFIG_MMC_SUNXI_SLOT_EXTRA=1
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CONFIG_USB0_VBUS_PIN="PB9"
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CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
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CONFIG_AXP_GPIO=y
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CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:24,pclk_khz:63000,le:32,ri:287,up:22,lo:12,hs:1,vs:1,sync:3,vmode:0"
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CONFIG_VIDEO_LCD_DCLK_PHASE=0
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CONFIG_VIDEO_LCD_POWER="PH8"
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CONFIG_VIDEO_LCD_BL_EN="PH7"
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CONFIG_VIDEO_LCD_BL_PWM="PB2"
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# CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set
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CONFIG_VIDEO_LCD_PANEL_LVDS=y
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CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SPL=y
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CONFIG_OF_BOARD_SETUP=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_CMD_GPIO=y
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CONFIG_USB_MUSB_HOST=y
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