u-boot/arch/arm/dts/bcm283x.dtsi
Henry Zhang a8798a6114 BCM283x ALT5 function for JTAG pins
BCM2835 ARM Peripherals doc shows gpio pins 4, 5, 6, 12 and 13 carry altenate
function, ALT5 for ARM JTAG

Signed-off-by: Henry Zhang <henryzhang62@yahoo.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 08:05:49 -05:00

640 lines
15 KiB
Text

#include <dt-bindings/pinctrl/bcm2835.h>
#include <dt-bindings/clock/bcm2835.h>
#include <dt-bindings/clock/bcm2835-aux.h>
#include <dt-bindings/gpio/gpio.h>
/* firmware-provided startup stubs live here, where the secondary CPUs are
* spinning.
*/
/memreserve/ 0x00000000 0x00001000;
/* This include file covers the common peripherals and configuration between
* bcm2835 and bcm2836 implementations, leaving the CPU configuration to
* bcm2835.dtsi and bcm2836.dtsi.
*/
/ {
compatible = "brcm,bcm2835";
model = "BCM2835";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
chosen {
bootargs = "earlyprintk console=ttyAMA0";
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <1000>;
thermal-sensors = <&thermal>;
trips {
cpu-crit {
temperature = <80000>;
hysteresis = <0>;
type = "critical";
};
};
cooling-maps {
};
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
timer@7e003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7e003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
/* This could be a reference to BCM2835_CLOCK_TIMER,
* but we don't have the driver using the common clock
* support yet.
*/
clock-frequency = <1000000>;
};
dma: dma@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xf00>;
interrupts = <1 16>,
<1 17>,
<1 18>,
<1 19>,
<1 20>,
<1 21>,
<1 22>,
<1 23>,
<1 24>,
<1 25>,
<1 26>,
/* dma channel 11-14 share one irq */
<1 27>,
<1 27>,
<1 27>,
<1 27>,
/* unused shared irq for all channels */
<1 28>;
interrupt-names = "dma0",
"dma1",
"dma2",
"dma3",
"dma4",
"dma5",
"dma6",
"dma7",
"dma8",
"dma9",
"dma10",
"dma11",
"dma12",
"dma13",
"dma14",
"dma-shared-all";
#dma-cells = <1>;
brcm,dma-channel-mask = <0x7f35>;
};
intc: interrupt-controller@7e00b200 {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
watchdog@7e100000 {
compatible = "brcm,bcm2835-pm-wdt";
reg = <0x7e100000 0x28>;
};
clocks: cprman@7e101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
reg = <0x7e101000 0x2000>;
/* CPRMAN derives almost everything from the
* platform's oscillator. However, the DSI
* pixel clocks come from the DSI analog PHY.
*/
clocks = <&clk_osc>,
<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
rng@7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
};
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
#mbox-cells = <0>;
};
gpio: gpio@7e200000 {
compatible = "brcm,bcm2835-gpio";
reg = <0x7e200000 0xb4>;
/*
* The GPIO IP block is designed for 3 banks of GPIOs.
* Each bank has a GPIO interrupt for itself.
* There is an overall "any bank" interrupt.
* In order, these are GIC interrupts 17, 18, 19, 20.
* Since the BCM2835 only has 2 banks, the 2nd bank
* interrupt output appears to be mirrored onto the
* 3rd bank's interrupt signal.
* So, a bank0 interrupt shows up on 17, 20, and
* a bank1 interrupt shows up on 18, 19, 20!
*/
interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
/* Defines pin muxing groups according to
* BCM2835-ARM-Peripherals.pdf page 102.
*
* While each pin can have its mux selected
* for various functions individually, some
* groups only make sense to switch to a
* particular function together.
*/
dpi_gpio0: dpi_gpio0 {
brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
emmc_gpio22: emmc_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
emmc_gpio34: emmc_gpio34 {
brcm,pins = <34 35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT3>;
brcm,pull = <BCM2835_PUD_OFF
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP
BCM2835_PUD_UP>;
};
emmc_gpio48: emmc_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
gpclk0_gpio4: gpclk0_gpio4 {
brcm,pins = <4>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio5: gpclk1_gpio5 {
brcm,pins = <5>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio42: gpclk1_gpio42 {
brcm,pins = <42>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk1_gpio44: gpclk1_gpio44 {
brcm,pins = <44>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk2_gpio6: gpclk2_gpio6 {
brcm,pins = <6>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
gpclk2_gpio43: gpclk2_gpio43 {
brcm,pins = <43>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio0: i2c0_gpio0 {
brcm,pins = <0 1>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio28: i2c0_gpio28 {
brcm,pins = <28 29>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c0_gpio44: i2c0_gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT1>;
};
i2c1_gpio2: i2c1_gpio2 {
brcm,pins = <2 3>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
i2c1_gpio44: i2c1_gpio44 {
brcm,pins = <44 45>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
i2c_slave_gpio18: i2c_slave_gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
jtag_gpio4: jtag_gpio4 {
brcm,pins = <4 5 6 12 13>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
jtag_gpio22: jtag_gpio22 {
brcm,pins = <22 23 24 25 26 27>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
pcm_gpio18: pcm_gpio18 {
brcm,pins = <18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pcm_gpio28: pcm_gpio28 {
brcm,pins = <28 29 30 31>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
pwm0_gpio12: pwm0_gpio12 {
brcm,pins = <12>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm0_gpio18: pwm0_gpio18 {
brcm,pins = <18>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
pwm0_gpio40: pwm0_gpio40 {
brcm,pins = <40>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio13: pwm1_gpio13 {
brcm,pins = <13>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio19: pwm1_gpio19 {
brcm,pins = <19>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
pwm1_gpio41: pwm1_gpio41 {
brcm,pins = <41>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
pwm1_gpio45: pwm1_gpio45 {
brcm,pins = <45>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
sdhost_gpio48: sdhost_gpio48 {
brcm,pins = <48 49 50 51 52 53>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi0_gpio7: spi0_gpio7 {
brcm,pins = <7 8 9 10 11>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi0_gpio35: spi0_gpio35 {
brcm,pins = <35 36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
spi1_gpio16: spi1_gpio16 {
brcm,pins = <16 17 18 19 20 21>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
spi2_gpio40: spi2_gpio40 {
brcm,pins = <40 41 42 43 44 45>;
brcm,function = <BCM2835_FSEL_ALT4>;
};
uart0_gpio14: uart0_gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT0>;
};
/* Separate from the uart0_gpio14 group
* because it conflicts with spi1_gpio16, and
* people often run uart0 on the two pins
* without flow control.
*/
uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_gpio32: uart0_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>;
};
uart0_gpio36: uart0_gpio36 {
brcm,pins = <36 37>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
brcm,pins = <38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio14: uart1_gpio14 {
brcm,pins = <14 15>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_gpio32: uart1_gpio32 {
brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_gpio40: uart1_gpio40 {
brcm,pins = <40 41>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
brcm,pins = <42 43>;
brcm,function = <BCM2835_FSEL_ALT5>;
};
};
uart0: serial@7e201000 {
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
reg = <0x7e201000 0x1000>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
};
sdhost: mmc@7e202000 {
compatible = "brcm,bcm2835-sdhost";
reg = <0x7e202000 0x100>;
interrupts = <2 24>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
dmas = <&dma 13>;
dma-names = "rx-tx";
status = "disabled";
};
i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = <0x7e203000 0x20>,
<0x7e101098 0x02>;
dmas = <&dma 2>,
<&dma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
spi: spi@7e204000 {
compatible = "brcm,bcm2835-spi";
reg = <0x7e204000 0x1000>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@7e205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pixelvalve@7e206000 {
compatible = "brcm,bcm2835-pixelvalve0";
reg = <0x7e206000 0x100>;
interrupts = <2 13>; /* pwa0 */
};
pixelvalve@7e207000 {
compatible = "brcm,bcm2835-pixelvalve1";
reg = <0x7e207000 0x100>;
interrupts = <2 14>; /* pwa1 */
};
dsi0: dsi@7e209000 {
compatible = "brcm,bcm2835-dsi0";
reg = <0x7e209000 0x78>;
interrupts = <2 4>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&clocks BCM2835_PLLA_DSI0>,
<&clocks BCM2835_CLOCK_DSI0E>,
<&clocks BCM2835_CLOCK_DSI0P>;
clock-names = "phy", "escape", "pixel";
clock-output-names = "dsi0_byte",
"dsi0_ddr2",
"dsi0_ddr";
};
thermal: thermal@7e212000 {
compatible = "brcm,bcm2835-thermal";
reg = <0x7e212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
#thermal-sensor-cells = <0>;
status = "disabled";
};
aux: aux@0x7e215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
reg = <0x7e215000 0x8>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
};
uart1: serial@7e215040 {
compatible = "brcm,bcm2835-aux-uart";
reg = <0x7e215040 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
status = "disabled";
};
spi1: spi@7e215080 {
compatible = "brcm,bcm2835-aux-spi";
reg = <0x7e215080 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@7e2150c0 {
compatible = "brcm,bcm2835-aux-spi";
reg = <0x7e2150c0 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm: pwm@7e20c000 {
compatible = "brcm,bcm2835-pwm";
reg = <0x7e20c000 0x28>;
clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clock-rates = <10000000>;
#pwm-cells = <2>;
status = "disabled";
};
sdhci: sdhci@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
clocks = <&clocks BCM2835_CLOCK_EMMC>;
status = "disabled";
};
hvs@7e400000 {
compatible = "brcm,bcm2835-hvs";
reg = <0x7e400000 0x6000>;
interrupts = <2 1>;
};
dsi1: dsi@7e700000 {
compatible = "brcm,bcm2835-dsi1";
reg = <0x7e700000 0x8c>;
interrupts = <2 12>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&clocks BCM2835_PLLD_DSI1>,
<&clocks BCM2835_CLOCK_DSI1E>,
<&clocks BCM2835_CLOCK_DSI1P>;
clock-names = "phy", "escape", "pixel";
clock-output-names = "dsi1_byte",
"dsi1_ddr2",
"dsi1_ddr";
status = "disabled";
};
i2c1: i2c@7e804000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e804000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@7e805000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e805000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
vec: vec@7e806000 {
compatible = "brcm,bcm2835-vec";
reg = <0x7e806000 0x1000>;
clocks = <&clocks BCM2835_CLOCK_VEC>;
interrupts = <2 27>;
status = "disabled";
};
pixelvalve@7e807000 {
compatible = "brcm,bcm2835-pixelvalve2";
reg = <0x7e807000 0x100>;
interrupts = <2 10>; /* pixelvalve */
};
hdmi: hdmi@7e902000 {
compatible = "brcm,bcm2835-hdmi";
reg = <0x7e902000 0x600>,
<0x7e808000 0x100>;
interrupts = <2 8>, <2 9>;
ddc = <&i2c2>;
clocks = <&clocks BCM2835_PLLH_PIX>,
<&clocks BCM2835_CLOCK_HSM>;
clock-names = "pixel", "hdmi";
dmas = <&dma 17>;
dma-names = "audio-rx";
status = "disabled";
};
usb: usb@7e980000 {
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
interrupts = <1 9>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clk_usb>;
clock-names = "otg";
phys = <&usbphy>;
phy-names = "usb2-phy";
};
v3d: v3d@7ec00000 {
compatible = "brcm,bcm2835-v3d";
reg = <0x7ec00000 0x1000>;
interrupts = <1 10>;
};
vc4: gpu {
compatible = "brcm,bcm2835-vc4";
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
/* The oscillator is the root of the clock tree. */
clk_osc: clock@3 {
compatible = "fixed-clock";
reg = <3>;
#clock-cells = <0>;
clock-output-names = "osc";
clock-frequency = <19200000>;
};
clk_usb: clock@4 {
compatible = "fixed-clock";
reg = <4>;
#clock-cells = <0>;
clock-output-names = "otg";
clock-frequency = <480000000>;
};
};
usbphy: phy {
compatible = "usb-nop-xceiv";
};
};
#include "bcm283x-uboot.dtsi"