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https://github.com/AsahiLinux/u-boot
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599474120a
The EQoS interface mode is now configured in common board_interface_eth_init() and called by EQoS MAC driver when appropriate. Drop the board side duplicates if the same functionality. Signed-off-by: Marek Vasut <marex@denx.de>
358 lines
9.4 KiB
C
358 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2022 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <env.h>
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#include <env_internal.h>
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#include <i2c_eeprom.h>
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#include <linux/bitfield.h>
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#include <malloc.h>
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#include <net.h>
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#include <miiphy.h>
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#include "lpddr4_timing.h"
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#include "../common/dh_common.h"
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#include "../common/dh_imx.h"
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DECLARE_GLOBAL_DATA_PTR;
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int mach_cpu_init(void)
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{
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icache_enable();
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return 0;
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}
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int board_phys_sdram_size(phys_size_t *size)
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{
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const u16 memsz[] = { 512, 1024, 1536, 2048, 3072, 4096, 6144, 8192 };
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u8 memcfg = dh_get_memcfg();
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*size = (u64)memsz[memcfg] << 20ULL;
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return 0;
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}
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output. */
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setbits_le32(&gpr->gpr[1], BIT(22));
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set_clk_enet(ENET_125MHZ);
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}
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static int dh_imx8_setup_ethaddr(void)
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{
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unsigned char enetaddr[6];
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if (dh_mac_is_in_env("ethaddr"))
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return 0;
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if (!dh_imx_get_mac_from_fuse(enetaddr))
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goto out;
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if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
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goto out;
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return -ENXIO;
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out:
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return eth_env_set_enetaddr("ethaddr", enetaddr);
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}
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static int dh_imx8_setup_eth1addr(void)
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{
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unsigned char enetaddr[6];
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if (dh_mac_is_in_env("eth1addr"))
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return 0;
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if (!dh_imx_get_mac_from_fuse(enetaddr))
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goto increment_out;
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if (!dh_get_mac_from_eeprom(enetaddr, "eeprom1"))
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goto out;
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/*
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* Populate second ethernet MAC from first ethernet EEPROM with MAC
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* address LSByte incremented by 1. This is only used on SoMs without
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* second ethernet EEPROM, i.e. early prototypes.
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*/
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if (!dh_get_mac_from_eeprom(enetaddr, "eeprom0"))
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goto increment_out;
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return -ENXIO;
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increment_out:
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enetaddr[5]++;
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out:
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return eth_env_set_enetaddr("eth1addr", enetaddr);
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}
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int dh_setup_mac_address(void)
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{
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int ret;
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ret = dh_imx8_setup_ethaddr();
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if (ret)
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printf("%s: Unable to setup ethaddr! ret = %d\n", __func__, ret);
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ret = dh_imx8_setup_eth1addr();
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if (ret)
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printf("%s: Unable to setup eth1addr! ret = %d\n", __func__, ret);
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return ret;
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}
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int board_init(void)
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{
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setup_fec();
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return 0;
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}
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int board_late_init(void)
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{
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dh_setup_mac_address();
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return 0;
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}
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enum env_location env_get_location(enum env_operation op, int prio)
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{
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return prio ? ENVL_UNKNOWN : ENVL_SPI_FLASH;
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}
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static const char *iomuxc_compat = "fsl,imx8mp-iomuxc";
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static const char *lan_compat = "ethernet-phy-id0007.c110";
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static const char *ksz_compat = "ethernet-phy-id0022.1642";
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static int dh_dt_patch_som_eqos(const void *fdt_blob)
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{
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const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24);
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int mac_node, mdio_node, iomuxc_node, ksz_node, lan_node, subnode;
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const char *mac_compat = "nxp,imx8mp-dwmac-eqos";
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void *blob = (void *)fdt_blob;
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const fdt32_t *clk_prop;
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bool is_gigabit;
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u32 handle;
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u32 clk[6];
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setbits_le32(mux, IOMUX_CONFIG_SION);
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is_gigabit = !(readl(GPIO1_BASE_ADDR) & BIT(24));
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clrbits_le32(mux, IOMUX_CONFIG_SION);
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/* Adjust EQoS node for Gigabit KSZ9131RNXI or Fast LAN8740Ai PHY */
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mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
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if (mac_node < 0)
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return 0;
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mdio_node = fdt_first_subnode(blob, mac_node);
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if (mdio_node < 0)
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return 0;
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/* KSZ9131RNXI */
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ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
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if (ksz_node < 0)
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return 0;
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/* LAN8740Ai */
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lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
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if (lan_node < 0)
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return 0;
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iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
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if (iomuxc_node < 0)
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return 0;
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/*
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* The code below adjusts the following DT properties:
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* - assigned-clock-parents .. 125 MHz RGMII / 50 MHz RMII ref clock
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* - assigned-clock-rates .... 125 MHz RGMII / 50 MHz RMII ref clock
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* - phy-handle .............. KSZ9131RNXI RGMII / LAN8740Ai RMII
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* - phy-mode ................ RGMII / RMII
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* - pinctrl-0 ............... RGMII / RMII
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* - PHY subnode status ...... "disabled"/"okay" per RGMII / RMII
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*/
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/* Perform all inplace changes first, string changes last. */
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clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
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if (!clk_prop)
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return 0;
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clk[0] = clk_prop[0];
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clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
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clk[2] = clk_prop[2];
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clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
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clk[4] = clk_prop[4];
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clk[5] = is_gigabit ? cpu_to_fdt32(IMX8MP_SYS_PLL2_125M) :
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cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
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fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
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clk, 6 * sizeof(u32));
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clk[0] = cpu_to_fdt32(0);
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clk[1] = cpu_to_fdt32(100000000);
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clk[2] = is_gigabit ? cpu_to_fdt32(125000000) :
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cpu_to_fdt32(50000000);
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fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
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clk, 3 * sizeof(u32));
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handle = fdt_get_phandle(blob, is_gigabit ? ksz_node : lan_node);
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fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
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fdt_for_each_subnode(subnode, blob, iomuxc_node) {
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if (!strstr(fdt_get_name(blob, subnode, NULL),
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is_gigabit ? "eqos-rgmii" : "eqos-rmii"))
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continue;
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handle = fdt_get_phandle(blob, subnode);
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fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
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break;
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}
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fdt_setprop_string(blob, mac_node, "phy-mode",
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is_gigabit ? "rgmii-id" : "rmii");
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mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
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mdio_node = fdt_first_subnode(blob, mac_node);
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ksz_node = fdt_node_offset_by_compatible(blob, mdio_node, ksz_compat);
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fdt_setprop_string(blob, ksz_node, "status",
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is_gigabit ? "okay" : "disabled");
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mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
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mdio_node = fdt_first_subnode(blob, mac_node);
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lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
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fdt_setprop_string(blob, lan_node, "status",
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is_gigabit ? "disabled" : "okay");
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return 0;
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}
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static int dh_dt_patch_som_fec(const void *fdt_blob)
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{
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const void __iomem *mux = (void __iomem *)IOMUXC_BASE_ADDR +
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FIELD_GET(MUX_CTRL_OFS_MASK, MX8MP_PAD_SAI1_TXFS__GPIO4_IO10);
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int mac_node, mdio_node, iomuxc_node, lan_node, phy_node, subnode;
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const char *mac_compat = "fsl,imx8mp-fec";
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void *blob = (void *)fdt_blob;
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const fdt32_t *clk_prop;
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bool is_gigabit;
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u32 handle;
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u32 clk[8];
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setbits_le32(mux, IOMUX_CONFIG_SION);
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is_gigabit = !(readl(GPIO4_BASE_ADDR) & BIT(10));
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clrbits_le32(mux, IOMUX_CONFIG_SION);
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/* Test for non-default SoM with 100/Full PHY attached to FEC */
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if (is_gigabit)
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return 0;
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/* Adjust FEC node for Fast LAN8740Ai PHY */
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mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
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if (mac_node < 0)
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return 0;
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/* Optional PHY pointed to by phy-handle, possibly on carrier board */
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phy_node = fdtdec_lookup_phandle(blob, mac_node, "phy-handle");
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if (phy_node > 0) {
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fdt_setprop_string(blob, phy_node, "status", "disabled");
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mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
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}
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mdio_node = fdt_first_subnode(blob, mac_node);
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if (mdio_node < 0)
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return 0;
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/* LAN8740Ai */
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lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
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if (lan_node < 0)
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return 0;
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iomuxc_node = fdt_node_offset_by_compatible(blob, -1, iomuxc_compat);
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if (iomuxc_node < 0)
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return 0;
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/*
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* The code below adjusts the following DT properties:
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* - assigned-clock-parents .. 50 MHz RMII ref clock
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* - assigned-clock-rates .... 50 MHz RMII ref clock
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* - phy-handle .............. LAN8740Ai RMII
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* - phy-mode ................ RMII
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* - pinctrl-0 ............... RMII
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* - PHY subnode status ...... "okay" for RMII PHY
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*/
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/* Perform all inplace changes first, string changes last. */
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clk_prop = fdt_getprop(blob, mac_node, "assigned-clock-parents", NULL);
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if (!clk_prop)
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return 0;
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clk[0] = clk_prop[0];
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clk[1] = cpu_to_fdt32(IMX8MP_SYS_PLL1_266M);
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clk[2] = clk_prop[2];
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clk[3] = cpu_to_fdt32(IMX8MP_SYS_PLL2_100M);
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clk[4] = clk_prop[4];
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clk[5] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
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clk[6] = clk_prop[6];
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clk[7] = cpu_to_fdt32(IMX8MP_SYS_PLL2_50M);
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fdt_setprop_inplace(blob, mac_node, "assigned-clock-parents",
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clk, 8 * sizeof(u32));
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clk[0] = cpu_to_fdt32(0);
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clk[1] = cpu_to_fdt32(100000000);
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clk[2] = cpu_to_fdt32(50000000);
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clk[3] = cpu_to_fdt32(0);
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fdt_setprop_inplace(blob, mac_node, "assigned-clock-rates",
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clk, 4 * sizeof(u32));
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handle = fdt_get_phandle(blob, lan_node);
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fdt_setprop_inplace_u32(blob, mac_node, "phy-handle", handle);
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fdt_for_each_subnode(subnode, blob, iomuxc_node) {
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if (!strstr(fdt_get_name(blob, subnode, NULL), "fec-rmii"))
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continue;
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handle = fdt_get_phandle(blob, subnode);
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fdt_setprop_inplace_u32(blob, mac_node, "pinctrl-0", handle);
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break;
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}
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fdt_setprop_string(blob, mac_node, "phy-mode", "rmii");
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mac_node = fdt_node_offset_by_compatible(blob, -1, mac_compat);
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mdio_node = fdt_first_subnode(blob, mac_node);
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lan_node = fdt_node_offset_by_compatible(blob, mdio_node, lan_compat);
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fdt_setprop_string(blob, lan_node, "status", "okay");
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return 0;
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}
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static int dh_dt_patch_som(const void *fdt_blob)
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{
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int ret;
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/* Do nothing if not i.MX8MP DHCOM SoM */
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ret = fdt_node_check_compatible(fdt_blob, 0, "dh,imx8mp-dhcom-som");
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if (ret)
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return 0;
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ret = dh_dt_patch_som_eqos(fdt_blob);
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if (ret)
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return ret;
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return dh_dt_patch_som_fec(fdt_blob);
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}
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int fdtdec_board_setup(const void *fdt_blob)
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{
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return dh_dt_patch_som(fdt_blob);
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}
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