mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-13 06:42:56 +00:00
aa36a74f0f
Fixes: bbda2ed584
("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
361 lines
9.7 KiB
C
361 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <bitfield.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <div64.h>
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#include <linux/delay.h>
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static struct rockchip_pll_rate_table rockchip_auto_table;
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#define PLL_MODE_MASK 0x3
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#define PLL_RK3328_MODE_MASK 0x1
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#define RK3036_PLLCON0_FBDIV_MASK 0xfff
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#define RK3036_PLLCON0_FBDIV_SHIFT 0
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#define RK3036_PLLCON0_POSTDIV1_MASK 0x7 << 12
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#define RK3036_PLLCON0_POSTDIV1_SHIFT 12
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#define RK3036_PLLCON1_REFDIV_MASK 0x3f
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#define RK3036_PLLCON1_REFDIV_SHIFT 0
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#define RK3036_PLLCON1_POSTDIV2_MASK 0x7 << 6
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#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
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#define RK3036_PLLCON1_DSMPD_MASK 0x1 << 12
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#define RK3036_PLLCON1_DSMPD_SHIFT 12
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#define RK3036_PLLCON2_FRAC_MASK 0xffffff
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#define RK3036_PLLCON2_FRAC_SHIFT 0
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#define RK3036_PLLCON1_PWRDOWN_SHIFT 13
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#define MHZ 1000000
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#define KHZ 1000
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enum {
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OSC_HZ = 24 * 1000000,
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VCO_MAX_HZ = 3200U * 1000000,
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VCO_MIN_HZ = 800 * 1000000,
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OUTPUT_MAX_HZ = 3200U * 1000000,
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OUTPUT_MIN_HZ = 24 * 1000000,
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};
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#define MIN_FOUTVCO_FREQ (800 * MHZ)
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#define MAX_FOUTVCO_FREQ (2000 * MHZ)
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int gcd(int m, int n)
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{
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int t;
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while (m > 0) {
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if (n > m) {
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t = m;
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m = n;
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n = t;
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} /* swap */
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m -= n;
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}
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return n;
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}
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/*
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* How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
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* Formulas also embedded within the Fractional PLL Verilog model:
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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* Where:
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* FOUTVCO = Fractional PLL non-divided output frequency
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* FOUTPOSTDIV = Fractional PLL divided output frequency
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* (output of second post divider)
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* FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
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* REFDIV = Fractional PLL input reference clock divider
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* FBDIV = Integer value programmed into feedback divide
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*
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*/
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static int rockchip_pll_clk_set_postdiv(ulong fout_hz,
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u32 *postdiv1,
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u32 *postdiv2,
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u32 *foutvco)
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{
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ulong freq;
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if (fout_hz < MIN_FOUTVCO_FREQ) {
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for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
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for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
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freq = fout_hz * (*postdiv1) * (*postdiv2);
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if (freq >= MIN_FOUTVCO_FREQ &&
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freq <= MAX_FOUTVCO_FREQ) {
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*foutvco = freq;
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return 0;
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}
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}
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}
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printf("Can't FIND postdiv1/2 to make fout=%lu in 800~2000M.\n",
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fout_hz);
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} else {
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*postdiv1 = 1;
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*postdiv2 = 1;
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}
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return 0;
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}
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static struct rockchip_pll_rate_table *
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rockchip_pll_clk_set_by_auto(ulong fin_hz,
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ulong fout_hz)
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{
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struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
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/* FIXME set postdiv1/2 always 1*/
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u32 foutvco = fout_hz;
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ulong fin_64, frac_64;
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u32 f_frac, postdiv1, postdiv2;
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ulong clk_gcd = 0;
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if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
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return NULL;
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rockchip_pll_clk_set_postdiv(fout_hz, &postdiv1, &postdiv2, &foutvco);
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rate_table->postdiv1 = postdiv1;
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rate_table->postdiv2 = postdiv2;
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rate_table->dsmpd = 1;
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if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
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fin_hz /= MHZ;
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foutvco /= MHZ;
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clk_gcd = gcd(fin_hz, foutvco);
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rate_table->refdiv = fin_hz / clk_gcd;
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rate_table->fbdiv = foutvco / clk_gcd;
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rate_table->frac = 0;
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debug("fin = %ld, fout = %ld, clk_gcd = %ld,\n",
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fin_hz, fout_hz, clk_gcd);
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debug("refdiv= %d,fbdiv= %d,postdiv1= %d,postdiv2= %d\n",
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rate_table->refdiv,
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rate_table->fbdiv, rate_table->postdiv1,
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rate_table->postdiv2);
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} else {
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debug("frac div,fin_hz = %ld,fout_hz = %ld\n",
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fin_hz, fout_hz);
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debug("frac get postdiv1 = %d, postdiv2 = %d, foutvco = %d\n",
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rate_table->postdiv1, rate_table->postdiv2, foutvco);
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clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
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rate_table->refdiv = fin_hz / MHZ / clk_gcd;
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rate_table->fbdiv = foutvco / MHZ / clk_gcd;
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debug("frac get refdiv = %d, fbdiv = %d\n",
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rate_table->refdiv, rate_table->fbdiv);
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rate_table->frac = 0;
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f_frac = (foutvco % MHZ);
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fin_64 = fin_hz;
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fin_64 = fin_64 / rate_table->refdiv;
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frac_64 = f_frac << 24;
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frac_64 = frac_64 / fin_64;
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rate_table->frac = frac_64;
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if (rate_table->frac > 0)
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rate_table->dsmpd = 0;
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debug("frac = %x\n", rate_table->frac);
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}
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return rate_table;
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}
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static const struct rockchip_pll_rate_table *
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rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate)
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{
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struct rockchip_pll_rate_table *rate_table = pll->rate_table;
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while (rate_table->rate) {
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if (rate_table->rate == rate)
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break;
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rate_table++;
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}
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if (rate_table->rate != rate)
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return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
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else
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return rate_table;
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}
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static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
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void __iomem *base, ulong pll_id,
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ulong drate)
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{
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const struct rockchip_pll_rate_table *rate;
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rate = rockchip_get_pll_settings(pll, drate);
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if (!rate) {
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printf("%s unsupport rate\n", __func__);
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return -EINVAL;
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}
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debug("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d\n",
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__func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv);
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debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n",
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__func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);
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/*
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* When power on or changing PLL setting,
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* we must force PLL into slow mode to ensure output stable clock.
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*/
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rk_clrsetreg(base + pll->mode_offset,
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pll->mode_mask << pll->mode_shift,
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RKCLK_PLL_MODE_SLOW << pll->mode_shift);
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/* Power down */
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rk_setreg(base + pll->con_offset + 0x4,
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1 << RK3036_PLLCON1_PWRDOWN_SHIFT);
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rk_clrsetreg(base + pll->con_offset,
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(RK3036_PLLCON0_POSTDIV1_MASK |
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RK3036_PLLCON0_FBDIV_MASK),
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(rate->postdiv1 << RK3036_PLLCON0_POSTDIV1_SHIFT) |
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rate->fbdiv);
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rk_clrsetreg(base + pll->con_offset + 0x4,
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(RK3036_PLLCON1_POSTDIV2_MASK |
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RK3036_PLLCON1_REFDIV_MASK),
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(rate->postdiv2 << RK3036_PLLCON1_POSTDIV2_SHIFT |
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rate->refdiv << RK3036_PLLCON1_REFDIV_SHIFT));
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if (!rate->dsmpd) {
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rk_clrsetreg(base + pll->con_offset + 0x4,
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RK3036_PLLCON1_DSMPD_MASK,
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rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
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writel((readl(base + pll->con_offset + 0x8) &
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(~RK3036_PLLCON2_FRAC_MASK)) |
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(rate->frac << RK3036_PLLCON2_FRAC_SHIFT),
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base + pll->con_offset + 0x8);
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}
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/* Power Up */
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rk_clrreg(base + pll->con_offset + 0x4,
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1 << RK3036_PLLCON1_PWRDOWN_SHIFT);
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/* waiting for pll lock */
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while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
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udelay(1);
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rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
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RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
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debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
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pll, readl(base + pll->con_offset),
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readl(base + pll->con_offset + 0x4),
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readl(base + pll->con_offset + 0x8),
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readl(base + pll->mode_offset));
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return 0;
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}
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static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
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void __iomem *base, ulong pll_id)
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{
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u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
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u32 con = 0, shift, mask;
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ulong rate;
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con = readl(base + pll->mode_offset);
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shift = pll->mode_shift;
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mask = pll->mode_mask << shift;
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switch ((con & mask) >> shift) {
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case RKCLK_PLL_MODE_SLOW:
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return OSC_HZ;
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case RKCLK_PLL_MODE_NORMAL:
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/* normal mode */
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con = readl(base + pll->con_offset);
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postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >>
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RK3036_PLLCON0_POSTDIV1_SHIFT;
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fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >>
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RK3036_PLLCON0_FBDIV_SHIFT;
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con = readl(base + pll->con_offset + 0x4);
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postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >>
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RK3036_PLLCON1_POSTDIV2_SHIFT;
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refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >>
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RK3036_PLLCON1_REFDIV_SHIFT;
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dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >>
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RK3036_PLLCON1_DSMPD_SHIFT;
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con = readl(base + pll->con_offset + 0x8);
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frac = (con & RK3036_PLLCON2_FRAC_MASK) >>
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RK3036_PLLCON2_FRAC_SHIFT;
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rate = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
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if (dsmpd == 0) {
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u64 frac_rate = OSC_HZ * (u64)frac;
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do_div(frac_rate, refdiv);
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frac_rate >>= 24;
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do_div(frac_rate, postdiv1);
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do_div(frac_rate, postdiv1);
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rate += frac_rate;
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}
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return rate;
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case RKCLK_PLL_MODE_DEEP:
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default:
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return 32768;
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}
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}
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ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll,
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void __iomem *base,
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ulong pll_id)
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{
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ulong rate = 0;
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switch (pll->type) {
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case pll_rk3036:
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pll->mode_mask = PLL_MODE_MASK;
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rate = rk3036_pll_get_rate(pll, base, pll_id);
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break;
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case pll_rk3328:
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pll->mode_mask = PLL_RK3328_MODE_MASK;
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rate = rk3036_pll_get_rate(pll, base, pll_id);
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break;
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default:
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printf("%s: Unknown pll type for pll clk %ld\n",
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__func__, pll_id);
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}
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return rate;
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}
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int rockchip_pll_set_rate(struct rockchip_pll_clock *pll,
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void __iomem *base, ulong pll_id,
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ulong drate)
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{
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int ret = 0;
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if (rockchip_pll_get_rate(pll, base, pll_id) == drate)
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return 0;
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switch (pll->type) {
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case pll_rk3036:
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pll->mode_mask = PLL_MODE_MASK;
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ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
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break;
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case pll_rk3328:
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pll->mode_mask = PLL_RK3328_MODE_MASK;
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ret = rk3036_pll_set_rate(pll, base, pll_id, drate);
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break;
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default:
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printf("%s: Unknown pll type for pll clk %ld\n",
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__func__, pll_id);
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}
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return ret;
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}
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const struct rockchip_cpu_rate_table *
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rockchip_get_cpu_settings(struct rockchip_cpu_rate_table *cpu_table,
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ulong rate)
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{
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struct rockchip_cpu_rate_table *ps = cpu_table;
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while (ps->rate) {
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if (ps->rate == rate)
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break;
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ps++;
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}
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if (ps->rate != rate)
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return NULL;
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else
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return ps;
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}
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