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32cfdd5163
The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.
As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Microchip Technology Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/microchip-mpfs-clock.h>
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#include <linux/err.h>
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#include "mpfs_clk.h"
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#define MPFS_MSSPLL_CLOCK "mpfs_msspll_clock"
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/* address offset of control registers */
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#define REG_MSSPLL_REF_CR 0x08u
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#define REG_MSSPLL_POSTDIV_CR 0x10u
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#define REG_MSSPLL_SSCG_2_CR 0x2Cu
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#define MSSPLL_FBDIV_SHIFT 0x00u
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#define MSSPLL_FBDIV_WIDTH 0x0Cu
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#define MSSPLL_REFDIV_SHIFT 0x08u
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#define MSSPLL_REFDIV_WIDTH 0x06u
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#define MSSPLL_POSTDIV_SHIFT 0x08u
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#define MSSPLL_POSTDIV_WIDTH 0x07u
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#define MSSPLL_FIXED_DIV 4u
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/**
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* struct mpfs_msspll_hw_clock
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* @id: index of the msspll clock
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* @name: the msspll clocks name
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* @reg_offset: offset to the core complex's output of the msspll
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* @shift: shift to the divider bit field of a msspll clock output
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* @width: width of the divider bit field of the msspll clock output
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* @flags: common clock framework flags
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* @prate: the reference clock rate
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* @hw: clock instance
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*/
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struct mpfs_msspll_hw_clock {
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void __iomem *base;
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unsigned int id;
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const char *name;
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u32 reg_offset;
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u32 shift;
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u32 width;
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u32 flags;
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u32 prate;
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struct clk hw;
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};
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#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
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static unsigned long mpfs_clk_msspll_recalc_rate(struct clk *hw)
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{
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struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
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void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
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void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
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void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
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u32 mult, ref_div, postdiv;
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unsigned long temp;
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mult = readl(mult_addr) >> MSSPLL_FBDIV_SHIFT;
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mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
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ref_div = readl(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
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postdiv = readl(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
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postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
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temp = msspll_hw->prate / (ref_div * MSSPLL_FIXED_DIV * postdiv);
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return temp * mult;
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}
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#define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \
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.id = _id, \
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.name = _name, \
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.shift = _shift, \
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.width = _width, \
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.reg_offset = _reg_offset, \
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.flags = _flags, \
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}
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static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
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CLK_PLL(CLK_MSSPLL, "clk_msspll", MSSPLL_FBDIV_SHIFT,
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MSSPLL_FBDIV_WIDTH, REG_MSSPLL_SSCG_2_CR, 0),
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};
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int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent)
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{
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int id, ret;
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const char *name;
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struct clk *hw;
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hw = &mpfs_msspll_clks[0].hw;
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mpfs_msspll_clks[0].base = base;
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mpfs_msspll_clks[0].prate = clk_get_rate(parent);
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name = mpfs_msspll_clks[0].name;
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ret = clk_register(hw, MPFS_MSSPLL_CLOCK, name, parent->dev->name);
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if (ret)
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ERR_PTR(ret);
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id = mpfs_msspll_clks[0].id;
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clk_dm(id, hw);
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return 0;
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}
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const struct clk_ops mpfs_msspll_clk_ops = {
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.get_rate = mpfs_clk_msspll_recalc_rate,
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};
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U_BOOT_DRIVER(mpfs_msspll_clock) = {
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.name = MPFS_MSSPLL_CLOCK,
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.id = UCLASS_CLK,
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.ops = &mpfs_msspll_clk_ops,
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};
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