mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
b1e81e67ee
Sync from Linux commit a188339ca5a3 ("Linux 5.2-rc1")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
657 lines
16 KiB
Text
657 lines
16 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/g12a-clkc.h>
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#include <dt-bindings/clock/g12a-aoclkc.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
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/ {
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compatible = "amlogic,g12a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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efuse: efuse {
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compatible = "amlogic,meson-gxbb-efuse";
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clocks = <&clkc CLKID_EFUSE>;
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#address-cells = <1>;
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#size-cells = <1>;
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read-only;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x0 0x10000000>;
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alignment = <0x0 0x400000>;
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linux,cma-default;
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};
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};
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sm: secure-monitor {
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compatible = "amlogic,meson-gxbb-sm";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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apb: bus@ff600000 {
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compatible = "simple-bus";
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reg = <0x0 0xff600000 0x0 0x200000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
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hdmi_tx: hdmi-tx@0 {
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compatible = "amlogic,meson-g12a-dw-hdmi";
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reg = <0x0 0x0 0x0 0x10000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
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resets = <&reset RESET_HDMITX_CAPB3>,
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<&reset RESET_HDMITX_PHY>,
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<&reset RESET_HDMITX>;
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reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
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clocks = <&clkc CLKID_HDMI>,
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<&clkc CLKID_HTX_PCLK>,
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<&clkc CLKID_VPU_INTR>;
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clock-names = "isfr", "iahb", "venci";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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/* VPU VENC Input */
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hdmi_tx_venc_port: port@0 {
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reg = <0>;
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hdmi_tx_in: endpoint {
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remote-endpoint = <&hdmi_tx_out>;
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};
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};
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/* TMDS Output */
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hdmi_tx_tmds_port: port@1 {
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reg = <1>;
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};
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};
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periphs: bus@34400 {
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compatible = "simple-bus";
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reg = <0x0 0x34400 0x0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
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periphs_pinctrl: pinctrl@40 {
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compatible = "amlogic,meson-g12a-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@40 {
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reg = <0x0 0x40 0x0 0x4c>,
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<0x0 0xe8 0x0 0x18>,
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<0x0 0x120 0x0 0x18>,
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<0x0 0x2c0 0x0 0x40>,
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<0x0 0x340 0x0 0x1c>;
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reg-names = "gpio",
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"pull",
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"pull-enable",
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"mux",
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"ds";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&periphs_pinctrl 0 0 86>;
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};
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cec_ao_a_h_pins: cec_ao_a_h {
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mux {
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groups = "cec_ao_a_h";
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function = "cec_ao_a_h";
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bias-disable;
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};
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};
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cec_ao_b_h_pins: cec_ao_b_h {
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mux {
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groups = "cec_ao_b_h";
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function = "cec_ao_b_h";
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bias-disable;
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};
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};
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hdmitx_ddc_pins: hdmitx_ddc {
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mux {
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groups = "hdmitx_sda",
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"hdmitx_sck";
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function = "hdmitx";
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bias-disable;
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};
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};
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hdmitx_hpd_pins: hdmitx_hpd {
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mux {
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groups = "hdmitx_hpd_in";
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function = "hdmitx";
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bias-disable;
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};
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};
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uart_a_pins: uart-a {
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mux {
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groups = "uart_a_tx",
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"uart_a_rx";
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function = "uart_a";
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bias-disable;
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};
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};
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uart_a_cts_rts_pins: uart-a-cts-rts {
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mux {
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groups = "uart_a_cts",
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"uart_a_rts";
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function = "uart_a";
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bias-disable;
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};
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};
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uart_b_pins: uart-b {
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mux {
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groups = "uart_b_tx",
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"uart_b_rx";
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function = "uart_b";
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bias-disable;
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};
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};
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uart_c_pins: uart-c {
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mux {
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groups = "uart_c_tx",
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"uart_c_rx";
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function = "uart_c";
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bias-disable;
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};
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};
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uart_c_cts_rts_pins: uart-c-cts-rts {
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mux {
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groups = "uart_c_cts",
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"uart_c_rts";
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function = "uart_c";
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bias-disable;
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};
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};
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};
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};
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usb2_phy0: phy@36000 {
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compatible = "amlogic,g12a-usb2-phy";
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reg = <0x0 0x36000 0x0 0x2000>;
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clocks = <&xtal>;
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clock-names = "xtal";
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resets = <&reset RESET_USB_PHY20>;
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reset-names = "phy";
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#phy-cells = <0>;
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};
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dmc: bus@38000 {
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compatible = "simple-bus";
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reg = <0x0 0x38000 0x0 0x400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
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canvas: video-lut@48 {
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compatible = "amlogic,canvas";
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reg = <0x0 0x48 0x0 0x14>;
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};
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};
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usb2_phy1: phy@3a000 {
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compatible = "amlogic,g12a-usb2-phy";
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reg = <0x0 0x3a000 0x0 0x2000>;
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clocks = <&xtal>;
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clock-names = "xtal";
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resets = <&reset RESET_USB_PHY21>;
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reset-names = "phy";
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#phy-cells = <0>;
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};
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hiu: bus@3c000 {
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compatible = "simple-bus";
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reg = <0x0 0x3c000 0x0 0x1400>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
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hhi: system-controller@0 {
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compatible = "amlogic,meson-gx-hhi-sysctrl",
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"simple-mfd", "syscon";
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reg = <0 0 0 0x400>;
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clkc: clock-controller {
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compatible = "amlogic,g12a-clkc";
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "xtal";
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};
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};
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};
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usb3_pcie_phy: phy@46000 {
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compatible = "amlogic,g12a-usb3-pcie-phy";
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reg = <0x0 0x46000 0x0 0x2000>;
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clocks = <&clkc CLKID_PCIE_PLL>;
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clock-names = "ref_clk";
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resets = <&reset RESET_PCIE_PHY>;
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reset-names = "phy";
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assigned-clocks = <&clkc CLKID_PCIE_PLL>;
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assigned-clock-rates = <100000000>;
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#phy-cells = <1>;
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};
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};
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aobus: bus@ff800000 {
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compatible = "simple-bus";
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reg = <0x0 0xff800000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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rti: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x0 0x0 0x0 0x100>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-g12a-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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clocks = <&xtal>, <&clkc CLKID_CLK81>;
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clock-names = "xtal", "mpeg-clk";
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};
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pwrc_vpu: power-controller-vpu {
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compatible = "amlogic,meson-g12a-pwrc-vpu";
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#power-domain-cells = <0>;
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amlogic,hhi-sysctrl = <&hhi>;
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resets = <&reset RESET_VIU>,
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<&reset RESET_VENC>,
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<&reset RESET_VCBUS>,
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<&reset RESET_BT656>,
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<&reset RESET_RDMA>,
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<&reset RESET_VENCI>,
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<&reset RESET_VENCP>,
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<&reset RESET_VDAC>,
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<&reset RESET_VDI6>,
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<&reset RESET_VENCL>,
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<&reset RESET_VID_LOCK>;
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clocks = <&clkc CLKID_VPU>,
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<&clkc CLKID_VAPB>;
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clock-names = "vpu", "vapb";
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/*
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* VPU clocking is provided by two identical clock paths
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* VPU_0 and VPU_1 muxed to a single clock by a glitch
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* free mux to safely change frequency while running.
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* Same for VAPB but with a final gate after the glitch free mux.
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*/
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assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_VPU>, /* Glitch free mux */
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<&clkc CLKID_VAPB_0_SEL>,
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<&clkc CLKID_VAPB_0>,
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<&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
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assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VPU_0>,
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<&clkc CLKID_FCLK_DIV4>,
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<0>, /* Do Nothing */
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<&clkc CLKID_VAPB_0>;
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assigned-clock-rates = <0>, /* Do Nothing */
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<666666666>,
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<0>, /* Do Nothing */
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<0>, /* Do Nothing */
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<250000000>,
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<0>; /* Do Nothing */
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};
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ao_pinctrl: pinctrl@14 {
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compatible = "amlogic,meson-g12a-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: bank@14 {
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reg = <0x0 0x14 0x0 0x8>,
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<0x0 0x1c 0x0 0x8>,
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<0x0 0x24 0x0 0x14>;
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reg-names = "mux",
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"ds",
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"gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&ao_pinctrl 0 0 15>;
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};
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uart_ao_a_pins: uart-a-ao {
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mux {
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groups = "uart_ao_a_tx",
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"uart_ao_a_rx";
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function = "uart_ao_a";
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bias-disable;
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};
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};
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uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
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mux {
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groups = "uart_ao_a_cts",
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"uart_ao_a_rts";
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function = "uart_ao_a";
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bias-disable;
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};
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};
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};
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};
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cec_AO: cec@100 {
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compatible = "amlogic,meson-gx-ao-cec";
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reg = <0x0 0x00100 0x0 0x14>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkc_AO CLKID_AO_CEC>;
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clock-names = "core";
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status = "disabled";
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};
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sec_AO: ao-secure@140 {
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compatible = "amlogic,meson-gx-ao-secure", "syscon";
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reg = <0x0 0x140 0x0 0x140>;
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amlogic,has-chip-id;
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};
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cecb_AO: cec@280 {
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compatible = "amlogic,meson-g12a-ao-cec";
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reg = <0x0 0x00280 0x0 0x1c>;
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interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
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clock-names = "oscin";
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status = "disabled";
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};
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uart_AO: serial@3000 {
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compatible = "amlogic,meson-gx-uart",
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"amlogic,meson-ao-uart";
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reg = <0x0 0x3000 0x0 0x18>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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uart_AO_B: serial@4000 {
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compatible = "amlogic,meson-gx-uart",
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"amlogic,meson-ao-uart";
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reg = <0x0 0x4000 0x0 0x18>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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saradc: adc@9000 {
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compatible = "amlogic,meson-g12a-saradc",
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"amlogic,meson-saradc";
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reg = <0x0 0x9000 0x0 0x48>;
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#io-channel-cells = <1>;
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interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>,
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<&clkc_AO CLKID_AO_SAR_ADC>,
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<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
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<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
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clock-names = "clkin", "core", "adc_clk", "adc_sel";
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status = "disabled";
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};
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};
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vpu: vpu@ff900000 {
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compatible = "amlogic,meson-g12a-vpu";
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reg = <0x0 0xff900000 0x0 0x100000>,
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<0x0 0xff63c000 0x0 0x1000>;
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reg-names = "vpu", "hhi";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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amlogic,canvas = <&canvas>;
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power-domains = <&pwrc_vpu>;
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/* CVBS VDAC output port */
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cvbs_vdac_port: port@0 {
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reg = <0>;
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};
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/* HDMI-TX output port */
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hdmi_tx_port: port@1 {
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reg = <1>;
|
|
|
|
hdmi_tx_out: endpoint {
|
|
remote-endpoint = <&hdmi_tx_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller@ffc01000 {
|
|
compatible = "arm,gic-400";
|
|
reg = <0x0 0xffc01000 0 0x1000>,
|
|
<0x0 0xffc02000 0 0x2000>,
|
|
<0x0 0xffc04000 0 0x2000>,
|
|
<0x0 0xffc06000 0 0x2000>;
|
|
interrupt-controller;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
};
|
|
|
|
cbus: bus@ffd00000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x0 0xffd00000 0x0 0x100000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
|
|
|
|
reset: reset-controller@1004 {
|
|
compatible = "amlogic,meson-g12a-reset",
|
|
"amlogic,meson-axg-reset";
|
|
reg = <0x0 0x1004 0x0 0x9c>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clk_msr: clock-measure@18000 {
|
|
compatible = "amlogic,meson-g12a-clk-measure";
|
|
reg = <0x0 0x18000 0x0 0x10>;
|
|
};
|
|
|
|
uart_C: serial@22000 {
|
|
compatible = "amlogic,meson-gx-uart";
|
|
reg = <0x0 0x22000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_B: serial@23000 {
|
|
compatible = "amlogic,meson-gx-uart";
|
|
reg = <0x0 0x23000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_A: serial@24000 {
|
|
compatible = "amlogic,meson-gx-uart";
|
|
reg = <0x0 0x24000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb: usb@ffe09000 {
|
|
status = "disabled";
|
|
compatible = "amlogic,meson-g12a-usb-ctrl";
|
|
reg = <0x0 0xffe09000 0x0 0xa0>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&clkc CLKID_USB>;
|
|
resets = <&reset RESET_USB>;
|
|
|
|
dr_mode = "otg";
|
|
|
|
phys = <&usb2_phy0>, <&usb2_phy1>,
|
|
<&usb3_pcie_phy PHY_TYPE_USB3>;
|
|
phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
|
|
|
|
dwc2: usb@ff400000 {
|
|
compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
|
|
reg = <0x0 0xff400000 0x0 0x40000>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
|
|
clock-names = "ddr";
|
|
phys = <&usb2_phy1>;
|
|
dr_mode = "peripheral";
|
|
g-rx-fifo-size = <192>;
|
|
g-np-tx-fifo-size = <128>;
|
|
g-tx-fifo-size = <128 128 16 16 16>;
|
|
};
|
|
|
|
dwc3: usb@ff500000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0xff500000 0x0 0x100000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
dr_mode = "host";
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,quirk-frame-length-adjustment;
|
|
};
|
|
};
|
|
|
|
mali: gpu@ffe40000 {
|
|
compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
|
|
reg = <0x0 0xffe40000 0x0 0x40000>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "gpu", "mmu", "job";
|
|
clocks = <&clkc CLKID_MALI>;
|
|
resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
|
|
|
|
/*
|
|
* Mali clocking is provided by two identical clock paths
|
|
* MALI_0 and MALI_1 muxed to a single clock by a glitch
|
|
* free mux to safely change frequency while running.
|
|
*/
|
|
assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
|
|
<&clkc CLKID_MALI_0>,
|
|
<&clkc CLKID_MALI>; /* Glitch free mux */
|
|
assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
|
|
<0>, /* Do Nothing */
|
|
<&clkc CLKID_MALI_0>;
|
|
assigned-clock-rates = <0>, /* Do Nothing */
|
|
<800000000>,
|
|
<0>; /* Do Nothing */
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
xtal: xtal-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "xtal";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
};
|