mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 22:33:18 +00:00
6d0f6bcf33
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
218 lines
5.8 KiB
C
218 lines
5.8 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
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* U-Boot port on RPXlite board
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*
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* DRAM related UPMA register values are modified.
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* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
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*/
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#include <common.h>
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#include "mpc8xx.h"
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/* ------------------------------------------------------------------------- */
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static long int dram_size (void);
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/* ------------------------------------------------------------------------- */
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#define MBYTE (1024*1024)
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#define DRAM_DELAY 0x00000379 /* DRAM delay count */
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#define _NOT_USED_ 0xFFFFCC25
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const uint sdram_table[] =
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{
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/* single read. (offset 0 in upm RAM) */
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0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
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0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
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/* burst read. (Offset 8 in upm RAM) */
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0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
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0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* single write. (Offset 0x18 in upm RAM) */
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0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* burst write. (Offset 0x20 in upm RAM) */
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0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
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0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Refresh cycle, offset 0x30 */
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0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Exception, 0ffset 0x3C */
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0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Return 1 for now.
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*
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*/
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int checkboard (void)
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{
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printf("Marel V37\n") ;
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return (0) ;
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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unsigned long temp;
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volatile int delay_cnt;
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long int ramsize;
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ramsize = dram_size();
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/* Refresh clock prescalar */
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memctl->memc_mptpr = 0x400 ;
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if( ramsize == 32*MBYTE )
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temp = 0xd0904110;
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else /* 16MB */
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temp = 0xd0802110;
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memctl->memc_mbmr = temp;
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upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/* Map controller banks 2 to the SDRAM bank */
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memctl->memc_or2 = 0xA00 | (0 - ramsize);
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memctl->memc_br2 = 0xC1;
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memctl->memc_mbmr = temp | 0x08;
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memctl->memc_mcr = 0x80804130;
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delay_cnt = 0;
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while( delay_cnt++ < DRAM_DELAY )
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;
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/* Run MRS command in location 5-8 of UPMB */
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memctl->memc_mbmr = temp | 0x04;
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memctl->memc_mar = 0x88;
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memctl->memc_mcr = 0x80804105;
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delay_cnt = 0;
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while( delay_cnt++ < DRAM_DELAY )
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;
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#ifdef CONFIG_CAN_DRIVER
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/* Initialize OR3 / BR3 */
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memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
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memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
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/* Initialize MBMR */
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memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
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/* Initialize UPMB for CAN: single read */
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memctl->memc_mdr = 0xFFFFC004;
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memctl->memc_mcr = 0x0100 | UPMA;
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memctl->memc_mdr = 0x0FFFD004;
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memctl->memc_mcr = 0x0101 | UPMA;
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memctl->memc_mdr = 0x0FFFC000;
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memctl->memc_mcr = 0x0102 | UPMA;
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memctl->memc_mdr = 0x3FFFC004;
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memctl->memc_mcr = 0x0103 | UPMA;
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memctl->memc_mdr = 0xFFFFDC05;
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memctl->memc_mcr = 0x0104 | UPMA;
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/* Initialize UPMB for CAN: single write */
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mcr = 0x0118 | UPMA;
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memctl->memc_mdr = 0xCFFCD004;
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memctl->memc_mcr = 0x0119 | UPMA;
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memctl->memc_mdr = 0x0FFCC000;
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memctl->memc_mcr = 0x011A | UPMA;
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memctl->memc_mdr = 0x7FFCC004;
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memctl->memc_mcr = 0x011B | UPMA;
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memctl->memc_mdr = 0xFFFDCC05;
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memctl->memc_mcr = 0x011C | UPMA;
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#endif /* CONFIG_CAN_DRIVER */
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return (dram_size());
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Find size of RAM from configuration pins.
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* The input pins that contain the memory size are also the debug port
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* pins. Normally they are configured as debug port pins. To be able
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* to read the memory configuration, we must deactivate the debug port
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* and enable the pcmcia input pins. Then return the register to
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* previous state.
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*/
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static long int dram_size ()
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf8xx_t *siu = &immap->im_siu_conf;
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volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
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long int i, memory=1;
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unsigned long siu_mcr;
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siu_mcr = siu->sc_siumcr;
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siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
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for(i=0; i<10; i++) i = i;
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memory = (pcm->pcmc_pipr>>12) & 0x3;
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siu->sc_siumcr = siu_mcr;
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switch( memory )
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{
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case 1:
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return( 32*MBYTE );
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case 2:
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return( 64*MBYTE );
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default:
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break;
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}
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return( 16*MBYTE );
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}
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