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550650ddd0
This patch removes the PPC4xx UART driver. Instead the common NS16550 driver is used, since all PPC4xx SoC's use this peripheral device. The file 4xx_uart.c now only implements the UART clock calculation function which also sets the SoC internal UART divisors. All PPC4xx board config headers are changed to use this common NS16550 driver now. Tested on these boards: acadia, canyonlands, katmai, kilauea, sequoia, zeus Signed-off-by: Stefan Roese <sr@denx.de>
108 lines
4.1 KiB
C
108 lines
4.1 KiB
C
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC405GP_H_
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#define _PPC405GP_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
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/* Memory mapped register */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
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/* DCR's */
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#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */
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#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */
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#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */
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#define OCM0_DSARC 0x001a /* OCM D-side address compare */
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#define OCM0_DSCNTL 0x001b /* OCM D-side control */
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#define CPC0_PLLMR 0x00b0 /* PLL mode register */
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#define CPC0_CR0 0x00b1 /* chip control register 0 */
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#define CPC0_CR1 0x00b2 /* chip control register 1 */
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#define CPC0_PSR 0x00b4 /* chip pin strapping reg */
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#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */
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#define CPC0_SR 0x00b8 /* Power management status */
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#define CPC0_ER 0x00b9 /* Power management enable */
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#define CPC0_FR 0x00ba /* Power management force */
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#define CPC0_ECR 0x00aa /* edge conditioner register */
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/* values for kiar register - indirect addressing of these regs */
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#define KCONF 0x40 /* decompression core config register */
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#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
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#define PLLMR_FWD_DIV_BYPASS 0xE0000000
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#define PLLMR_FWD_DIV_3 0xA0000000
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#define PLLMR_FWD_DIV_4 0x80000000
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#define PLLMR_FWD_DIV_6 0x40000000
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#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
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#define PLLMR_FB_DIV_1 0x02000000
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#define PLLMR_FB_DIV_2 0x04000000
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#define PLLMR_FB_DIV_3 0x06000000
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#define PLLMR_FB_DIV_4 0x08000000
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#define PLLMR_TUNING_MASK 0x01F80000
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#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
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#define PLLMR_CPU_PLB_DIV_1 0x00000000
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#define PLLMR_CPU_PLB_DIV_2 0x00020000
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#define PLLMR_CPU_PLB_DIV_3 0x00040000
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#define PLLMR_CPU_PLB_DIV_4 0x00060000
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#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
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#define PLLMR_OPB_PLB_DIV_1 0x00000000
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#define PLLMR_OPB_PLB_DIV_2 0x00008000
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#define PLLMR_OPB_PLB_DIV_3 0x00010000
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#define PLLMR_OPB_PLB_DIV_4 0x00018000
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#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
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#define PLLMR_PCI_PLB_DIV_1 0x00000000
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#define PLLMR_PCI_PLB_DIV_2 0x00002000
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#define PLLMR_PCI_PLB_DIV_3 0x00004000
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#define PLLMR_PCI_PLB_DIV_4 0x00006000
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#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
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#define PLLMR_EXB_PLB_DIV_2 0x00000000
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#define PLLMR_EXB_PLB_DIV_3 0x00000800
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#define PLLMR_EXB_PLB_DIV_4 0x00001000
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#define PLLMR_EXB_PLB_DIV_5 0x00001800
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/* definitions for PPC405GPr (new mode strapping) */
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#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
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#define PSR_PLL_FWD_MASK 0xC0000000
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#define PSR_PLL_FDBACK_MASK 0x30000000
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#define PSR_PLL_TUNING_MASK 0x0E000000
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#define PSR_PLB_CPU_MASK 0x01800000
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#define PSR_OPB_PLB_MASK 0x00600000
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#define PSR_PCI_PLB_MASK 0x00180000
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#define PSR_EB_PLB_MASK 0x00060000
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#define PSR_ROM_WIDTH_MASK 0x00018000
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#define PSR_ROM_LOC 0x00004000
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#define PSR_PCI_ASYNC_EN 0x00001000
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#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
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#define PSR_PCI_ARBIT_EN 0x00000400
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#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
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#endif /* _PPC405GP_H_ */
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