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0fd3d91152
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
196 lines
5.3 KiB
C
196 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) EETS GmbH, 2017, Felix Brack <f.brack@eets.ch>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <linux/libfdt.h>
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#include <asm/io.h>
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struct single_pdata {
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fdt_addr_t base; /* first configuration register */
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int offset; /* index of last configuration register */
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u32 mask; /* configuration-value mask bits */
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int width; /* configuration register bit width */
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bool bits_per_mux;
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};
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struct single_fdt_pin_cfg {
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fdt32_t reg; /* configuration register offset */
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fdt32_t val; /* configuration register value */
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};
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struct single_fdt_bits_cfg {
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fdt32_t reg; /* configuration register offset */
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fdt32_t val; /* configuration register value */
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fdt32_t mask; /* configuration register mask */
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};
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/**
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* single_configure_pins() - Configure pins based on FDT data
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*
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* @dev: Pointer to single pin configuration device which is the parent of
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* the pins node holding the pin configuration data.
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* @pins: Pointer to the first element of an array of register/value pairs
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* of type 'struct single_fdt_pin_cfg'. Each such pair describes the
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* the pin to be configured and the value to be used for configuration.
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* This pointer points to a 'pinctrl-single,pins' property in the
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* device-tree.
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* @size: Size of the 'pins' array in bytes.
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* The number of register/value pairs in the 'pins' array therefore
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* equals to 'size / sizeof(struct single_fdt_pin_cfg)'.
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*/
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static int single_configure_pins(struct udevice *dev,
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const struct single_fdt_pin_cfg *pins,
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int size)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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int count = size / sizeof(struct single_fdt_pin_cfg);
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phys_addr_t n, reg;
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u32 val;
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for (n = 0; n < count; n++, pins++) {
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reg = fdt32_to_cpu(pins->reg);
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if ((reg < 0) || (reg > pdata->offset)) {
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dev_dbg(dev, " invalid register offset 0x%pa\n", ®);
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continue;
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}
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reg += pdata->base;
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val = fdt32_to_cpu(pins->val) & pdata->mask;
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switch (pdata->width) {
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case 16:
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writew((readw(reg) & ~pdata->mask) | val, reg);
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break;
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case 32:
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writel((readl(reg) & ~pdata->mask) | val, reg);
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break;
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default:
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dev_warn(dev, "unsupported register width %i\n",
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pdata->width);
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continue;
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}
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dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val);
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}
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return 0;
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}
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static int single_configure_bits(struct udevice *dev,
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const struct single_fdt_bits_cfg *pins,
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int size)
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{
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struct single_pdata *pdata = dev_get_plat(dev);
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int count = size / sizeof(struct single_fdt_bits_cfg);
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phys_addr_t n, reg;
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u32 val, mask;
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for (n = 0; n < count; n++, pins++) {
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reg = fdt32_to_cpu(pins->reg);
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if ((reg < 0) || (reg > pdata->offset)) {
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dev_dbg(dev, " invalid register offset 0x%pa\n", ®);
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continue;
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}
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reg += pdata->base;
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mask = fdt32_to_cpu(pins->mask);
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val = fdt32_to_cpu(pins->val) & mask;
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switch (pdata->width) {
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case 16:
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writew((readw(reg) & ~mask) | val, reg);
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break;
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case 32:
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writel((readl(reg) & ~mask) | val, reg);
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break;
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default:
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dev_warn(dev, "unsupported register width %i\n",
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pdata->width);
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continue;
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}
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dev_dbg(dev, " reg/val 0x%pa/0x%08x\n", ®, val);
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}
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return 0;
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}
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static int single_set_state(struct udevice *dev,
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struct udevice *config)
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{
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const struct single_fdt_pin_cfg *prop;
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const struct single_fdt_bits_cfg *prop_bits;
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int len;
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prop = dev_read_prop(config, "pinctrl-single,pins", &len);
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if (prop) {
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dev_dbg(dev, "configuring pins for %s\n", config->name);
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if (len % sizeof(struct single_fdt_pin_cfg)) {
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dev_dbg(dev, " invalid pin configuration in fdt\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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single_configure_pins(dev, prop, len);
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return 0;
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}
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/* pinctrl-single,pins not found so check for pinctrl-single,bits */
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prop_bits = dev_read_prop(config, "pinctrl-single,bits", &len);
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if (prop_bits) {
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dev_dbg(dev, "configuring pins for %s\n", config->name);
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if (len % sizeof(struct single_fdt_bits_cfg)) {
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dev_dbg(dev, " invalid bits configuration in fdt\n");
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return -FDT_ERR_BADSTRUCTURE;
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}
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single_configure_bits(dev, prop_bits, len);
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return 0;
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}
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/* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
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return len;
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}
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static int single_of_to_plat(struct udevice *dev)
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{
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fdt_addr_t addr;
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u32 of_reg[2];
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int res;
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struct single_pdata *pdata = dev_get_plat(dev);
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pdata->width =
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dev_read_u32_default(dev, "pinctrl-single,register-width", 0);
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res = dev_read_u32_array(dev, "reg", of_reg, 2);
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if (res)
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return res;
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pdata->offset = of_reg[1] - pdata->width / 8;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE) {
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dev_dbg(dev, "no valid base register address\n");
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return -EINVAL;
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}
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pdata->base = addr;
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pdata->mask = dev_read_u32_default(dev, "pinctrl-single,function-mask",
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0xffffffff);
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pdata->bits_per_mux = dev_read_bool(dev, "pinctrl-single,bit-per-mux");
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return 0;
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}
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const struct pinctrl_ops single_pinctrl_ops = {
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.set_state = single_set_state,
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};
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static const struct udevice_id single_pinctrl_match[] = {
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{ .compatible = "pinctrl-single" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(single_pinctrl) = {
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.name = "single-pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = single_pinctrl_match,
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.ops = &single_pinctrl_ops,
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.plat_auto = sizeof(struct single_pdata),
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.of_to_plat = single_of_to_plat,
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};
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