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58c86c7d1d
Fix the wrong mapping between the DDR I/O control registers on AM33XX SoCs and the software representation in the SPL code. The most recent public TRM defines the following DDR I/O control registers offsets: * ddr_cmd0_ioctrl : offset 0x44E11404 * ddr_cmd1_ioctrl : offset 0x44E11408 * ddr_cmd2_ioctrl : offset 0x44E1140C * ddr_data0_ioctrl: offset 0x44E11440 * ddr_data1_ioctrl: offset 0x44E11444 While the struct ddr_cmdtctrl has also some reserved bits in the beginning. The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc. Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because of this mapping mismatch. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk> |
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| .. | ||
| clock.h | ||
| clocks_am33xx.h | ||
| cpu.h | ||
| ddr_defs.h | ||
| elm.h | ||
| gpio.h | ||
| hardware.h | ||
| hardware_am33xx.h | ||
| hardware_ti814x.h | ||
| i2c.h | ||
| mem.h | ||
| mmc_host_def.h | ||
| mux.h | ||
| mux_am33xx.h | ||
| mux_ti814x.h | ||
| omap.h | ||
| omap_gpmc.h | ||
| spl.h | ||
| sys_proto.h | ||