mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 19:23:07 +00:00
1b2f4697c0
Introduce the basic AM62 SoC description dtsi files describing most peripherals as per kernel dts. Signed-off-by: Gowtham Tammana <g-tammana@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
103 lines
1.9 KiB
Text
103 lines
1.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Device Tree Source for AM625 SoC family in Quad core configuration
|
|
*
|
|
* TRM: https://www.ti.com/lit/pdf/spruiv7
|
|
*
|
|
* Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "k3-am62.dtsi"
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu-map {
|
|
cluster0: cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&cpu1>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&cpu2>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <&cpu3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu0: cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x000>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
i-cache-size = <0x8000>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x001>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
i-cache-size = <0x8000>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x002>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
i-cache-size = <0x8000>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
|
|
cpu3: cpu@3 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x003>;
|
|
device_type = "cpu";
|
|
enable-method = "psci";
|
|
i-cache-size = <0x8000>;
|
|
i-cache-line-size = <64>;
|
|
i-cache-sets = <256>;
|
|
d-cache-size = <0x8000>;
|
|
d-cache-line-size = <64>;
|
|
d-cache-sets = <128>;
|
|
next-level-cache = <&L2_0>;
|
|
};
|
|
};
|
|
|
|
L2_0: l2-cache0 {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-size = <0x40000>;
|
|
cache-line-size = <64>;
|
|
cache-sets = <512>;
|
|
};
|
|
};
|