mirror of
https://github.com/AsahiLinux/u-boot
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c03f4da187
The DT properties for the "enable-arbiter" and "keep-config" config
knobs were previously named inconsistently:
- The u-boot driver used "nand-enable-arbiter" and "nand-keep-config"
names, without Marvell prefixes.
- The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter"
does not exist anymore in recent kernels, but it also used to be
"marvell,nand-enable-arbiter").
- The device trees almost all use "marvell," prefixed names, except for
one single instance of "nand-enable-arbiter" without vendor prefix.
This commit standardizes on the vendor prefixed version, making the
u-boot driver read from DT props "marvell,nand-enable-arbiter" and
"marvell,nand-keep-config". The one device tree using the unprefixed
version is also changed to use the new naming.
This has the side effect of making the previously no-op "marvell,"
config knobs already present in some DTs actually do something. This was
likely the original intention of the DT authors, but note that this
commit was not tested on every single impacted board.
Signed-off-by: Pierre Bourdon <delroth@gmail.com>
359 lines
10 KiB
Text
359 lines
10 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016- 2021 Marvell International Ltd.
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*/
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/*
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* Generic Device Tree describing Marvell Armada CP-110 device
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*/
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#include <dt-bindings/comphy/comphy_data.h>
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#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
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#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
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#define CP110_PCIEx_REG0_BASE(iface) \
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(CP110_BASE + 0x600000 + (iface) * 0x20000)
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#define CP110_PCIEx_REG1_BASE(iface) \
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(CP110_PCIEx_CPU_MEM_BASE(iface) + CP110_PCIE_MEM_SIZE(iface))
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#define CP110_PCIE_EP_REG_BASE(iface) (CP110_BASE + 0x600000 + \
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(iface) * 0x4000)
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/ {
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CP110_NAME {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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config-space {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
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CP110_LABEL(mdio): mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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device-name = CP110_STRING_LABEL(mdio);
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status = "disabled";
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};
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CP110_LABEL(xmdio): mdio@12a600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,xmdio";
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reg = <0x12a600 0x200>;
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device-name = CP110_STRING_LABEL(xmdio);
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status = "disabled";
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};
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CP110_LABEL(sar-reg) {
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compatible = "marvell,sample-at-reset-common",
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"marvell,sample-at-reset-cp110";
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reg = <0x400200 0x8>;
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sar-driver = "cp110_sar";
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sar-name = CP110_STRING_LABEL(sar);
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status = "okay";
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};
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CP110_LABEL(syscon0): system-controller@440000 {
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compatible = "marvell,cp110-system-controller0",
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"syscon";
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reg = <0x440000 0x1000>;
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#clock-cells = <2>;
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core-clock-output-names =
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"cpm-apll", "cpm-ppv2-core", "cpm-eip",
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"cpm-core", "cpm-nand-core";
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gate-clock-output-names =
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"cpm-audio", "cpm-communit", "cpm-nand",
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"cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
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"cpm-mg-core", "cpm-xor1", "cpm-xor0",
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"cpm-gop-dp", "none", "cpm-pcie_x10",
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"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
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"cpm-sata", "cpm-sata-usb", "cpm-main",
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"cpm-sd-mmc", "none", "none",
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"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
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"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
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};
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CP110_LABEL(pinctl): pinctl@440000 {
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compatible = "marvell,mvebu-pinctrl";
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reg = <0x440000 0x20>;
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pin-count = <63>;
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max-func = <0xf>;
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};
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CP110_LABEL(gpio0): gpio@440100 {
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compatible = "marvell,orion-gpio";
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reg = <0x440100 0x40>;
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ngpios = <32>;
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gpiobase = <20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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CP110_LABEL(gpio1): gpio@440140 {
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compatible = "marvell,orion-gpio";
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reg = <0x440140 0x40>;
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ngpios = <31>;
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gpiobase = <52>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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CP110_LABEL(sata0): sata@540000 {
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compatible = "marvell,armada-8k-ahci";
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reg = <0x540000 0x30000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(syscon0) 1 15>;
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status = "disabled";
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};
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CP110_LABEL(usb3_0): usb3@500000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x500000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(syscon0) 1 22>;
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status = "disabled";
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};
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CP110_LABEL(usb3_1): usb3@510000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x510000 0x4000>;
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dma-coherent;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(syscon0) 1 23>;
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status = "disabled";
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};
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CP110_LABEL(spi0): spi@700600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700600 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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cell-index = <1>;
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spi-max-frequency = <50000000>;
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clocks = <&CP110_LABEL(syscon0) 0 3>;
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status = "disabled";
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};
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CP110_LABEL(spi1): spi@700680 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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spi-max-frequency = <50000000>;
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clocks = <&CP110_LABEL(syscon0) 1 21>;
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status = "disabled";
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};
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CP110_LABEL(i2c0): i2c@701000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(syscon0) 1 21>;
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status = "disabled";
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};
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CP110_LABEL(i2c1): i2c@701100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(syscon0) 1 21>;
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status = "disabled";
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};
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CP110_LABEL(mss_i2c0): i2c@211000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x211000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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CP110_LABEL(comphy): comphy@441000 {
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compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
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reg = <0x441000 0x8>,
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<0x120000 0x8>;
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mux-bitcount = <4>;
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max-lanes = <6>;
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};
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CP110_LABEL(utmi): utmi@580000 {
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compatible = "marvell,mvebu-utmi";
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reg = <0x580000 0xc>; /* utmi-common-pll */
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#address-cells = <1>;
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#size-cells = <1>;
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CP110_LABEL(utmi0): utmi@58000c {
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compatible = "marvell,mvebu-utmi-2.6.0";
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reg = <0x58000c 0x100>,/* utmi-unit */
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<0x440420 0x4>, /* usb-cfg */
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<0x440440 0x4>; /* utmi-cfg */
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utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
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status = "disabled";
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};
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CP110_LABEL(utmi1): utmi@58100c {
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compatible = "marvell,mvebu-utmi-2.6.0";
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reg = <0x58100c 0x100>,/* utmi-unit */
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<0x440420 0x4>, /* usb-cfg */
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<0x440444 0x4>; /* utmi-cfg */
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utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
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status = "disabled";
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};
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};
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CP110_LABEL(sdhci0): sdhci@780000 {
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compatible = "marvell,armada-8k-sdhci";
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reg = <0x780000 0x300>;
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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CP110_LABEL(nand): nand@720000 {
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compatible = "marvell,armada-8k-nand-controller",
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"marvell,armada370-nand-controller";
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reg = <0x720000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&CP110_LABEL(syscon0) 1 2>;
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marvell,nand-enable-arbiter;
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num-cs = <1>;
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nand-ecc-strength = <8>;
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nand-ecc-step-size = <512>;
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marvell,system-controller = <&CP110_LABEL(syscon0)>;
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status = "disabled";
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};
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CP110_LABEL(ethernet): ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&CP110_LABEL(syscon0) 1 3>, <&CP110_LABEL(syscon0) 1 9>, <&CP110_LABEL(syscon0) 1 5>;
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clock-names = "pp_clk", "gop_clk", "mg_clk";
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status = "disabled";
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dma-coherent;
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CP110_LABEL(eth0): eth0 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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CP110_LABEL(eth1): eth1 {
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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CP110_LABEL(eth2): eth2 {
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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};
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CP110_LABEL(pcie0): pcie0@600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg =
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<U64_TO_U32_H(CP110_PCIEx_REG0_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(0)) 0 0x10000>,
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/* Last 512KB of mem space */
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<U64_TO_U32_H(CP110_PCIEx_REG1_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(0)) 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges =
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/* non-prefetchable memory */
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<CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(0))
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U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(0)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(0))
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U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(0))
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U64_TO_U32_H(CP110_PCIE_MEM_SIZE(0)) U64_TO_U32_L(CP110_PCIE_MEM_SIZE(0))>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&CP110_LABEL(syscon0) 1 13>;
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status = "disabled";
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};
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CP110_LABEL(pcie1): pcie1@620000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg =
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<U64_TO_U32_H(CP110_PCIEx_REG0_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(1)) 0 0x10000>,
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/* Last 512KB of mem space */
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<U64_TO_U32_H(CP110_PCIEx_REG1_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(1)) 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges =
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/* non-prefetchable memory */
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<CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(1))
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U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(1))
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U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(1))
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U64_TO_U32_L(CP110_PCIE_MEM_SIZE(1))>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&CP110_LABEL(syscon0) 1 11>;
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status = "disabled";
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};
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CP110_LABEL(pcie2): pcie2@640000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg =
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<U64_TO_U32_H(CP110_PCIEx_REG0_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(2)) 0 0x10000>,
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/* Last 64KB of mem space */
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<U64_TO_U32_H(CP110_PCIEx_REG1_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(2)) 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0 0xff>;
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ranges =
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/* non-prefetchable memory */
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<CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(2))
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U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(2))
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U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(2))
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U64_TO_U32_L(CP110_PCIE_MEM_SIZE(2))>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&CP110_LABEL(syscon0) 1 12>;
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status = "disabled";
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};
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};
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};
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