mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
ce90654d1c
There are several changes which happen in mainline kernel which should get also to U-Boot. Here is the list of patches from the kernel: - ARM: zynq: Fix leds subnode name for zc702/zybo-z7 - arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 - arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111 - arm64: dts: zynqmp: Wire up the DisplayPort subsystem - arm64: dts: zynqmp: Add DisplayPort subsystem - arm64: dts: zynqmp: Add DPDMA node - arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106 - arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111 - arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 - arm64: dts: zynqmp-zcu100-revC: correct interrupt flags - arm64: dts: xilinx: align GPIO hog names with dtschema - arm64: zynqmp: Add Xilinx AES node - dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA but also some other changes have been done. - Using only one compatible string for adxl345 on zturn - Remove Xilinx internal DP bindings - Remove USB3.0 serdes configurations - Remove SATA serdes configuration for zc1232 - Resort nvmem_firmware - Update nand compatible string - Aling power-domains property for sd0/1 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
428 lines
6.9 KiB
Text
428 lines
6.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2011 - 2015 Xilinx
|
|
* Copyright (C) 2012 National Instruments Corp.
|
|
*/
|
|
/dts-v1/;
|
|
#include "zynq-7000.dtsi"
|
|
|
|
/ {
|
|
model = "Xilinx ZC702 board";
|
|
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
|
|
|
|
aliases {
|
|
ethernet0 = &gem0;
|
|
i2c0 = &i2c0;
|
|
serial0 = &uart1;
|
|
spi0 = &qspi;
|
|
mmc0 = &sdhci0;
|
|
usb0 = &usb0;
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x40000000>;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "";
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
gpio-keys {
|
|
compatible = "gpio-keys";
|
|
autorepeat;
|
|
sw14 {
|
|
label = "sw14";
|
|
gpios = <&gpio0 12 0>;
|
|
linux,code = <108>; /* down */
|
|
wakeup-source;
|
|
autorepeat;
|
|
};
|
|
sw13 {
|
|
label = "sw13";
|
|
gpios = <&gpio0 14 0>;
|
|
linux,code = <103>; /* up */
|
|
wakeup-source;
|
|
autorepeat;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led-ds23 {
|
|
label = "ds23";
|
|
gpios = <&gpio0 10 0>;
|
|
linux,default-trigger = "heartbeat";
|
|
};
|
|
};
|
|
|
|
usb_phy0: phy0 {
|
|
compatible = "usb-nop-xceiv";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
&amba {
|
|
ocm: sram@fffc0000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0xfffc0000 0x10000>;
|
|
};
|
|
};
|
|
|
|
&can0 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_can0_default>;
|
|
};
|
|
|
|
&clkc {
|
|
ps-clk-frequency = <33333333>;
|
|
};
|
|
|
|
&gem0 {
|
|
status = "okay";
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðernet_phy>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gem0_default>;
|
|
phy-reset-gpio = <&gpio0 11 0>;
|
|
phy-reset-active-low;
|
|
|
|
ethernet_phy: ethernet-phy@7 {
|
|
reg = <7>;
|
|
device_type = "ethernet-phy";
|
|
};
|
|
};
|
|
|
|
&gpio0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpio0_default>;
|
|
};
|
|
|
|
&i2c0 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default", "gpio";
|
|
pinctrl-0 = <&pinctrl_i2c0_default>;
|
|
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
|
scl-gpios = <&gpio0 50 0>;
|
|
sda-gpios = <&gpio0 51 0>;
|
|
|
|
i2c-mux@74 {
|
|
compatible = "nxp,pca9548";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x74>;
|
|
|
|
i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
si570: clock-generator@5d {
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
temperature-stability = <50>;
|
|
reg = <0x5d>;
|
|
factory-fout = <156250000>;
|
|
clock-frequency = <148500000>;
|
|
};
|
|
};
|
|
|
|
i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
adv7511: hdmi-tx@39 {
|
|
compatible = "adi,adv7511";
|
|
reg = <0x39>;
|
|
adi,input-depth = <8>;
|
|
adi,input-colorspace = "yuv422";
|
|
adi,input-clock = "1x";
|
|
adi,input-style = <3>;
|
|
adi,input-justification = "right";
|
|
};
|
|
};
|
|
|
|
i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
eeprom@54 {
|
|
compatible = "atmel,24c08";
|
|
reg = <0x54>;
|
|
};
|
|
};
|
|
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
gpio@21 {
|
|
compatible = "ti,tca6416";
|
|
reg = <0x21>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
};
|
|
};
|
|
|
|
i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
rtc@51 {
|
|
compatible = "nxp,pcf8563";
|
|
reg = <0x51>;
|
|
};
|
|
};
|
|
|
|
i2c@7 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
hwmon@34 {
|
|
compatible = "ti,ucd9248";
|
|
reg = <0x34>;
|
|
};
|
|
hwmon@35 {
|
|
compatible = "ti,ucd9248";
|
|
reg = <0x35>;
|
|
};
|
|
hwmon@36 {
|
|
compatible = "ti,ucd9248";
|
|
reg = <0x36>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&pinctrl0 {
|
|
pinctrl_can0_default: can0-default {
|
|
mux {
|
|
function = "can0";
|
|
groups = "can0_9_grp";
|
|
};
|
|
|
|
conf {
|
|
groups = "can0_9_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO46";
|
|
bias-high-impedance;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO47";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pinctrl_gem0_default: gem0-default {
|
|
mux {
|
|
function = "ethernet0";
|
|
groups = "ethernet0_0_grp";
|
|
};
|
|
|
|
conf {
|
|
groups = "ethernet0_0_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <4>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
|
|
bias-high-impedance;
|
|
low-power-disable;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
|
|
bias-disable;
|
|
low-power-enable;
|
|
};
|
|
|
|
mux-mdio {
|
|
function = "mdio0";
|
|
groups = "mdio0_0_grp";
|
|
};
|
|
|
|
conf-mdio {
|
|
groups = "mdio0_0_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pinctrl_gpio0_default: gpio0-default {
|
|
mux {
|
|
function = "gpio0";
|
|
groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
|
|
"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
|
|
"gpio0_13_grp", "gpio0_14_grp";
|
|
};
|
|
|
|
conf {
|
|
groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
|
|
"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
|
|
"gpio0_13_grp", "gpio0_14_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
|
|
conf-pull-up {
|
|
pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
|
|
bias-pull-up;
|
|
};
|
|
|
|
conf-pull-none {
|
|
pins = "MIO7", "MIO8";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pinctrl_i2c0_default: i2c0-default {
|
|
mux {
|
|
groups = "i2c0_10_grp";
|
|
function = "i2c0";
|
|
};
|
|
|
|
conf {
|
|
groups = "i2c0_10_grp";
|
|
bias-pull-up;
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
};
|
|
|
|
pinctrl_i2c0_gpio: i2c0-gpio {
|
|
mux {
|
|
groups = "gpio0_50_grp", "gpio0_51_grp";
|
|
function = "gpio0";
|
|
};
|
|
|
|
conf {
|
|
groups = "gpio0_50_grp", "gpio0_51_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
};
|
|
|
|
pinctrl_sdhci0_default: sdhci0-default {
|
|
mux {
|
|
groups = "sdio0_2_grp";
|
|
function = "sdio0";
|
|
};
|
|
|
|
conf {
|
|
groups = "sdio0_2_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
bias-disable;
|
|
};
|
|
|
|
mux-cd {
|
|
groups = "gpio0_0_grp";
|
|
function = "sdio0_cd";
|
|
};
|
|
|
|
conf-cd {
|
|
groups = "gpio0_0_grp";
|
|
bias-high-impedance;
|
|
bias-pull-up;
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
|
|
mux-wp {
|
|
groups = "gpio0_15_grp";
|
|
function = "sdio0_wp";
|
|
};
|
|
|
|
conf-wp {
|
|
groups = "gpio0_15_grp";
|
|
bias-high-impedance;
|
|
bias-pull-up;
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
};
|
|
|
|
pinctrl_uart1_default: uart1-default {
|
|
mux {
|
|
groups = "uart1_10_grp";
|
|
function = "uart1";
|
|
};
|
|
|
|
conf {
|
|
groups = "uart1_10_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO49";
|
|
bias-high-impedance;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO48";
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
pinctrl_usb0_default: usb0-default {
|
|
mux {
|
|
groups = "usb0_0_grp";
|
|
function = "usb0";
|
|
};
|
|
|
|
conf {
|
|
groups = "usb0_0_grp";
|
|
slew-rate = <0>;
|
|
io-standard = <1>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO29", "MIO31", "MIO36";
|
|
bias-high-impedance;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
|
|
"MIO35", "MIO37", "MIO38", "MIO39";
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
&qspi {
|
|
u-boot,dm-pre-reloc;
|
|
status = "okay";
|
|
};
|
|
|
|
&sdhci0 {
|
|
u-boot,dm-pre-reloc;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
|
};
|
|
|
|
&uart1 {
|
|
u-boot,dm-pre-reloc;
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1_default>;
|
|
};
|
|
|
|
&usb0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
usb-phy = <&usb_phy0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb0_default>;
|
|
};
|