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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
57 lines
1.1 KiB
C
57 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@amd.com>
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*/
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#ifndef _ASM_ARCH_SYS_PROTO_H
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#define _ASM_ARCH_SYS_PROTO_H
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#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
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#define KEY_PTR_LEN 32
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#define IV_SIZE 12
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#define RSA_KEY_SIZE 512
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#define MODULUS_LEN 512
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#define PRIV_EXPO_LEN 512
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#define PUB_EXPO_LEN 4
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#define ZYNQMP_SHA3_INIT 1
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#define ZYNQMP_SHA3_UPDATE 2
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#define ZYNQMP_SHA3_FINAL 4
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#define ZYNQMP_SHA3_SIZE 48
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#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
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#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
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#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
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#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
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#define ZYNQMP_FPGA_BIT_NS 5
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#define ZYNQMP_FPGA_AUTH_DDR 1
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enum {
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IDCODE,
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VERSION,
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IDCODE2,
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};
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enum {
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ZYNQMP_SILICON_V1,
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ZYNQMP_SILICON_V2,
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ZYNQMP_SILICON_V3,
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ZYNQMP_SILICON_V4,
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};
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enum {
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TCM_LOCK,
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TCM_SPLIT,
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};
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unsigned int zynqmp_get_silicon_version(void);
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void initialize_tcm(bool mode);
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void mem_map_fill(void);
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#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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void tcm_init(u8 mode);
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#endif
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#endif /* _ASM_ARCH_SYS_PROTO_H */
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