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01c7714a7b
Use the ZDMA channel 0 to initialize the DRAM banks. This avoid spurious ECC errors that can occur when accessing unitialized memory. The feature is enabled by setting the option CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT and providing the following data: SPL_ZYNQMP_DRAM_BANK1_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK1_LEN : len of memory to initialize (hex) SPL_ZYNQMP_DRAM_BANK2_BASE: start of memory to initialize SPL_ZYNQMP_DRAM_BANK2_LEN : len of memory to initialize (hex) Setting SPL_ZYNQMP_DRAM_BANK_LEN to 0 takes no action. Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
163 lines
4.9 KiB
C
163 lines
4.9 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright(c) 2015 - 2020 Xilinx, Inc.
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*
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* Jorge Ramirez-Ortiz <jorge@foundries.io>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/ecc_spl_init.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#define ZDMA_TRANSFER_MAX_LEN (0x3FFFFFFFU - 7U)
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#define ZDMA_CH_STATUS ((ADMA_CH0_BASEADDR) + 0x0000011CU)
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#define ZDMA_CH_STATUS_STATE_MASK 0x00000003U
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#define ZDMA_CH_STATUS_STATE_DONE 0x00000000U
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#define ZDMA_CH_STATUS_STATE_ERR 0x00000003U
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#define ZDMA_CH_CTRL0 ((ADMA_CH0_BASEADDR) + 0x00000110U)
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#define ZDMA_CH_CTRL0_POINT_TYPE_MASK (u32)0x00000040U
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#define ZDMA_CH_CTRL0_POINT_TYPE_NORMAL (u32)0x00000000U
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#define ZDMA_CH_CTRL0_MODE_MASK (u32)0x00000030U
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#define ZDMA_CH_CTRL0_MODE_WR_ONLY (u32)0x00000010U
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#define ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT ((ADMA_CH0_BASEADDR) + 0x00000188U)
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#define ZDMA_CH_WR_ONLY_WORD0 ((ADMA_CH0_BASEADDR) + 0x00000148U)
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#define ZDMA_CH_WR_ONLY_WORD1 ((ADMA_CH0_BASEADDR) + 0x0000014CU)
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#define ZDMA_CH_WR_ONLY_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000150U)
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#define ZDMA_CH_WR_ONLY_WORD3 ((ADMA_CH0_BASEADDR) + 0x00000154U)
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#define ZDMA_CH_DST_DSCR_WORD0 ((ADMA_CH0_BASEADDR) + 0x00000138U)
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#define ZDMA_CH_DST_DSCR_WORD0_LSB_MASK 0xFFFFFFFFU
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#define ZDMA_CH_DST_DSCR_WORD1 ((ADMA_CH0_BASEADDR) + 0x0000013CU)
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#define ZDMA_CH_DST_DSCR_WORD1_MSB_MASK 0x0001FFFFU
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#define ZDMA_CH_SRC_DSCR_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000130U)
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#define ZDMA_CH_DST_DSCR_WORD2 ((ADMA_CH0_BASEADDR) + 0x00000140U)
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#define ZDMA_CH_CTRL2 ((ADMA_CH0_BASEADDR) + 0x00000200U)
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#define ZDMA_CH_CTRL2_EN_MASK 0x00000001U
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#define ZDMA_CH_ISR ((ADMA_CH0_BASEADDR) + 0x00000100U)
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#define ZDMA_CH_ISR_DMA_DONE_MASK 0x00000400U
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#define ECC_INIT_VAL_WORD 0xDEADBEEFU
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#define ZDMA_IDLE_TIMEOUT_USEC 1000000
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#define ZDMA_DONE_TIMEOUT_USEC 5000000
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static void ecc_zdma_restore(void)
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{
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/* Restore reset values for the DMA registers used */
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writel(ZDMA_CH_CTRL0, 0x00000080U);
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writel(ZDMA_CH_WR_ONLY_WORD0, 0x00000000U);
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writel(ZDMA_CH_WR_ONLY_WORD1, 0x00000000U);
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writel(ZDMA_CH_WR_ONLY_WORD2, 0x00000000U);
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writel(ZDMA_CH_WR_ONLY_WORD3, 0x00000000U);
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writel(ZDMA_CH_DST_DSCR_WORD0, 0x00000000U);
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writel(ZDMA_CH_DST_DSCR_WORD1, 0x00000000U);
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writel(ZDMA_CH_SRC_DSCR_WORD2, 0x00000000U);
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writel(ZDMA_CH_DST_DSCR_WORD2, 0x00000000U);
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writel(ZDMA_CH_CTRL0_TOTAL_BYTE_COUNT, 0x00000000U);
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}
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static void ecc_dram_bank_init(u64 addr, u64 len)
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{
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bool retry = true;
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u32 timeout;
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u64 bytes;
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u32 size;
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u64 src;
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u32 reg;
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if (!len)
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return;
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retry:
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bytes = len;
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src = addr;
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ecc_zdma_restore();
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while (bytes > 0) {
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size = bytes > ZDMA_TRANSFER_MAX_LEN ?
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ZDMA_TRANSFER_MAX_LEN : (u32)bytes;
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/* Wait until the DMA is in idle state */
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timeout = ZDMA_IDLE_TIMEOUT_USEC;
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do {
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udelay(1);
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reg = readl(ZDMA_CH_STATUS);
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reg &= ZDMA_CH_STATUS_STATE_MASK;
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if (!timeout--) {
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puts("error, ECC DMA failed to idle\n");
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goto done;
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}
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} while ((reg != ZDMA_CH_STATUS_STATE_DONE) &&
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(reg != ZDMA_CH_STATUS_STATE_ERR));
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/* Enable Simple (Write Only) Mode */
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reg = readl(ZDMA_CH_CTRL0);
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reg &= (ZDMA_CH_CTRL0_POINT_TYPE_MASK |
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ZDMA_CH_CTRL0_MODE_MASK);
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reg |= (ZDMA_CH_CTRL0_POINT_TYPE_NORMAL |
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ZDMA_CH_CTRL0_MODE_WR_ONLY);
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writel(reg, ZDMA_CH_CTRL0);
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/* Fill in the data to be written */
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writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD0);
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writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD1);
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writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD2);
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writel(ECC_INIT_VAL_WORD, ZDMA_CH_WR_ONLY_WORD3);
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/* Write Destination Address */
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writel((u32)(src & ZDMA_CH_DST_DSCR_WORD0_LSB_MASK),
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ZDMA_CH_DST_DSCR_WORD0);
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writel((u32)((src >> 32) & ZDMA_CH_DST_DSCR_WORD1_MSB_MASK),
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ZDMA_CH_DST_DSCR_WORD1);
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/* Size to be Transferred. Recommended to set both src and dest sizes */
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writel(size, ZDMA_CH_SRC_DSCR_WORD2);
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writel(size, ZDMA_CH_DST_DSCR_WORD2);
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/* DMA Enable */
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reg = readl(ZDMA_CH_CTRL2);
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reg |= ZDMA_CH_CTRL2_EN_MASK;
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writel(reg, ZDMA_CH_CTRL2);
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/* Check the status of the transfer by polling on DMA Done */
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timeout = ZDMA_DONE_TIMEOUT_USEC;
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do {
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udelay(1);
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reg = readl(ZDMA_CH_ISR);
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reg &= ZDMA_CH_ISR_DMA_DONE_MASK;
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if (!timeout--) {
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puts("error, ECC DMA timeout\n");
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goto done;
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}
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} while (reg != ZDMA_CH_ISR_DMA_DONE_MASK);
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/* Clear DMA status */
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reg = readl(ZDMA_CH_ISR);
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reg |= ZDMA_CH_ISR_DMA_DONE_MASK;
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writel(ZDMA_CH_ISR_DMA_DONE_MASK, ZDMA_CH_ISR);
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/* Read the channel status for errors */
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reg = readl(ZDMA_CH_STATUS);
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if (reg == ZDMA_CH_STATUS_STATE_ERR) {
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if (retry) {
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retry = false;
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goto retry;
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}
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puts("error, ECC DMA error\n");
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break;
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}
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bytes -= size;
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src += size;
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}
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done:
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ecc_zdma_restore();
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}
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void zynqmp_ecc_init(void)
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{
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ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK1_BASE,
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CONFIG_SPL_ZYNQMP_DRAM_BANK1_LEN);
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ecc_dram_bank_init(CONFIG_SPL_ZYNQMP_DRAM_BANK2_BASE,
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CONFIG_SPL_ZYNQMP_DRAM_BANK2_LEN);
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}
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