mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
5d90836cb5
The default U-Boot environment variables and design are all set up for the MAIN R5FSS cluster to be in Split-mode. This is the setting used when the dts nodes were originally added in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit468ec2f3ef("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The modes for the MAIN R5FSS cluster got switched back to LockStep mode by mistake in commitfa09b12dc5("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") in v2022.01-rc1. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes:fa09b12dc5("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") Signed-off-by: Suman Anna <s-anna@ti.com>
198 lines
2.7 KiB
Text
198 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
/ {
|
|
chosen {
|
|
stdout-path = "serial2:115200n8";
|
|
tick-timer = &timer1;
|
|
};
|
|
|
|
aliases {
|
|
ethernet0 = &cpsw_port1;
|
|
i2c0 = &wkup_i2c0;
|
|
i2c1 = &mcu_i2c0;
|
|
i2c2 = &mcu_i2c1;
|
|
i2c3 = &main_i2c0;
|
|
};
|
|
};
|
|
|
|
&cbass_main {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_navss {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&cbass_mcu_wakeup {
|
|
u-boot,dm-spl;
|
|
|
|
timer1: timer@40400000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x40400000 0x0 0x80>;
|
|
ti,timer-alwon;
|
|
clock-frequency = <250000000>;
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
chipid@43000014 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
mcu_navss: bus@28380000 {
|
|
u-boot,dm-spl;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
ringacc@2b800000 {
|
|
reg = <0x0 0x2b800000 0x0 0x400000>,
|
|
<0x0 0x2b000000 0x0 0x400000>,
|
|
<0x0 0x28590000 0x0 0x100>,
|
|
<0x0 0x2a500000 0x0 0x40000>,
|
|
<0x0 0x28440000 0x0 0x40000>;
|
|
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
dma-controller@285c0000 {
|
|
reg = <0x0 0x285c0000 0x0 0x100>,
|
|
<0x0 0x284c0000 0x0 0x4000>,
|
|
<0x0 0x2a800000 0x0 0x40000>,
|
|
<0x0 0x284a0000 0x0 0x4000>,
|
|
<0x0 0x2aa00000 0x0 0x40000>,
|
|
<0x0 0x28400000 0x0 0x2000>;
|
|
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
|
|
"tchanrt", "rflow";
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
};
|
|
|
|
&secure_proxy_main {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&dmsc {
|
|
u-boot,dm-spl;
|
|
k3_sysreset: sysreset-controller {
|
|
compatible = "ti,sci-sysreset";
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&k3_pds {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&k3_clks {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&k3_reset {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&wkup_pmx0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_pmx0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_uart0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&mcu_uart0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_sdhci0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_sdhci1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&wkup_i2c0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_i2c0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_i2c0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&exp2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&mcu_cpsw {
|
|
reg = <0x0 0x46000000 0x0 0x200000>,
|
|
<0x0 0x40f00200 0x0 0x8>;
|
|
reg-names = "cpsw_nuss", "mac_efuse";
|
|
/delete-property/ ranges;
|
|
|
|
cpsw-phy-sel@40f04040 {
|
|
compatible = "ti,am654-cpsw-phy-sel";
|
|
reg= <0x0 0x40f04040 0x0 0x4>;
|
|
reg-names = "gmii-sel";
|
|
};
|
|
};
|
|
|
|
&main_usbss0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&usbss0 {
|
|
u-boot,dm-spl;
|
|
ti,usb2-only;
|
|
};
|
|
|
|
&usb0 {
|
|
dr_mode = "peripheral";
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&mcu_fss0_hpb0_pins_default {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&fss {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&hbmc {
|
|
u-boot,dm-spl;
|
|
|
|
flash@0,0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&hbmc_mux {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&serdes_ln_ctrl {
|
|
u-boot,mux-autoprobe;
|
|
};
|
|
|
|
&usb_serdes_mux {
|
|
u-boot,mux-autoprobe;
|
|
};
|
|
|
|
&serdes0 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&main_r5fss0 {
|
|
ti,cluster-mode = <0>;
|
|
};
|