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u-boot/arch/arm/dts/imx8mp-verdin.dts
Marcel Ziswiler 2bc2f817ce board: toradex: add verdin imx8m plus support 
This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB
IT V1.0B module. They are strapped to boot from eFuses which are factory
fused to properly boot from their on-module eMMC. U-Boot supports
booting from the on-module eMMC only, SDP support is disabled for now
due to missing i.MX 8M Plus USB support.

Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet both on-module eQoS and FEC (requires PHY on carrier board)
- GPIOs
- I2C

Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper

ATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.

Boot:
U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
Quad die, dual rank failed, attempting dual die, single rank configuration.
Normal Boot
WDT:   Started watchdog@30280000 with servicing (60s timeout)
Trying to boot from BOOTROM
Find img info 0x&48025a00, size 872
Need continue download 1024
Download 779264, Total size 780424
NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
NOTICE:  BL31: Built : 16:52:37, Aug 26 2021

U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)

CPU:   Freescale i.MX8MP[8] rev1.1 at 1200 MHz
Reset cause: POR
DRAM:  8 GiB
Core:  78 devices, 18 uclasses, devicetree: separate
WDT:   Started watchdog@30280000 with servicing (60s timeout)
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
Setting variant to wifi
Net:   Hard-coding pdata->enetaddr
eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
Hit any key to stop autoboot:  0
Verdin iMX8MP #

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-07 16:33:22 +01:00

639 lines
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2022 Toradex
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus";
compatible = "toradex,verdin-imx8mp", "fsl,imx8mp";
aliases {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier;
eeprom2 = &eeprom_mipi_dsi;
/* Ethernet aliases to ensure correct MAC addresses */
ethernet0 = &eqos;
ethernet1 = &fec;
};
chosen {
bootargs = "console=ttymxc2,115200 earlycon";
stdout-path = &uart3;
};
reg_usb1_host_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* USB_2_EN */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus>;
regulator-always-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb1_host_vbus";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; /* SD_1_PWR_EN */
off-on-delay-us = <12000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "V3.3_SD";
startup-delay-us = <100>;
};
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
};
&fec {
fsl,magic-packet;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
};
&gpio2 {
regulator-ethphy {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
line-name = "reg_ethphy";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_eth>;
};
ctrl_sleep_moci {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* Verdin PMIC_I2C */
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: pca9450@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
regulators {
#address-cells = <1>;
/* Run/Standby voltage */
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
pca9450,pmic-buck2-uses-i2c-dvs;
#size-cells = <0>;
buck1_reg: regulator@0 {
reg = <0>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck1";
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck2_reg: regulator@1 {
reg = <1>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck2";
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
};
buck4_reg: regulator@3 {
reg = <3>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck4";
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck5_reg: regulator@4 {
reg = <4>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck5";
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
buck6_reg: regulator@5 {
reg = <5>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "buck6";
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
};
ldo1_reg: regulator@6 {
reg = <6>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo1";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
};
ldo2_reg: regulator@7 {
reg = <7>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo2";
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <800000>;
};
ldo3_reg: regulator@8 {
reg = <8>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo3";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo4_reg: regulator@9 {
reg = <9>;
regulator-always-on;
regulator-boot-on;
regulator-compatible = "ldo4";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
};
ldo5_reg: regulator@10 { /* +V3.3_1.8_SD */
reg = <10>;
regulator-compatible = "ldo5";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
};
};
/* Epson RX8130 real time clock on carrier board */
rtc: rx8130@32 {
compatible = "epson,rx8130";
reg = <0x32>;
};
eeprom_module: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x50>;
};
};
/* Verdin I2C2 DSI */
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
};
/* Verdin I2C4 CSI */
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
#gpio-cells = <2>;
gpio-controller;
reg = <0x20>;
};
};
/* Verdin I2C1 */
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
status = "okay";
/* EEPROM on MIPI-DSI to HDMI adapter */
eeprom_mipi_dsi: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x50>;
};
/* EEPROM on Verdin Development board */
eeprom_carrier: eeprom@57 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x57>;
};
};
&snvs_pwrkey {
status = "okay";
};
/* Verdin UART3 */
&uart3 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
adp-disable;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* Verdin SDIO 1 */
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
/* On-module eMMC */
&usdhc3 {
bus-width = <8>;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
status = "okay";
};
&wdog1 {
fsl,ext-reset-output;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, <&pinctrl_gpio3>,
<&pinctrl_gpio4>, <&pinctrl_gpio5>, <&pinctrl_gpio6>,
<&pinctrl_gpio7>, <&pinctrl_gpio8>;
pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4 /* SODIMM 256 */
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
>;
};
/* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184 /* SODIMM 206 */
>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x184 /* SODIMM 208 */
>;
};
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184 /* SODIMM 210 */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184 /* SODIMM 212 */
>;
};
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184 /* SODIMM 216 */
>;
};
pinctrl_gpio6: gpio6grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184 /* SODIMM 218 */
>;
};
pinctrl_gpio7: gpio7grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184 /* SODIMM 220 */
>;
};
pinctrl_gpio8: gpio8grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184 /* SODIMM 222 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c1_gpio: i2c1grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c4_gpio: i2c4grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3
>;
};
pinctrl_reg_eth: regethgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x41
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
>;
};
pinctrl_usb1_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2grp-gpio {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x1d1
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};
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