mirror of
https://github.com/AsahiLinux/u-boot
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94c30f9c8f
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár <pali@kernel.org>
663 lines
17 KiB
Text
663 lines
17 KiB
Text
/*
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* Device Tree Include file for Marvell Armada 375 family SoC
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Armada 375 family SoC";
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compatible = "marvell,armada375";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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clocks {
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/* 2 GHz fixed main PLL */
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mainpll: mainpll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000000>;
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};
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/* 25 MHz reference crystal */
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refclk: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-375-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts-extended = <&mpic 3>;
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};
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soc {
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compatible = "marvell,armada375-mbus", "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&gic>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs0 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs1 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs2 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs3 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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internal-regs {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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L2: cache-controller@8000 {
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compatible = "arm,pl310-cache";
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reg = <0x8000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,double-linefill-incr = <1>;
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arm,double-linefill-wrap = <0>;
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arm,double-linefill = <1>;
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prefetch-data = <1>;
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};
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scu@c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xc000 0x58>;
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};
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timer@c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xc600 0x20>;
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interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
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clocks = <&coreclk 2>;
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};
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gic: interrupt-controller@d000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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interrupt-controller;
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reg = <0xd000 0x1000>,
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<0xc100 0x100>;
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0xc0054 0x4>;
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clocks = <&gateclk 19>;
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};
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/* Network controller */
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ethernet@f0000 {
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compatible = "marvell,armada-375-pp2";
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reg = <0xf0000 0xa000>, /* Packet Processor regs */
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<0xc0000 0x3060>, /* LMS regs */
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<0xc4000 0x100>, /* eth0 regs */
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<0xc5000 0x100>; /* eth1 regs */
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clocks = <&gateclk 3>, <&gateclk 19>;
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clock-names = "pp_clk", "gop_clk";
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status = "disabled";
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eth0: eth0@c4000 {
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <0>;
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status = "disabled";
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};
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eth1: eth1@c5000 {
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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port-id = <1>;
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status = "disabled";
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};
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};
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rtc@10300 {
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compatible = "marvell,orion-rtc";
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reg = <0x10300 0x20>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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spi0: spi@10600 {
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compatible = "marvell,armada-375-spi",
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"marvell,orion-spi";
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reg = <0x10600 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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spi1: spi@10680 {
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compatible = "marvell,armada-375-spi",
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"marvell,orion-spi";
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reg = <0x10680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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pinctrl {
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compatible = "marvell,mv88f6720-pinctrl";
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reg = <0x18000 0x24>;
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i2c0_pins: i2c0-pins {
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marvell,pins = "mpp14", "mpp15";
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marvell,function = "i2c0";
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};
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i2c1_pins: i2c1-pins {
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marvell,pins = "mpp61", "mpp62";
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marvell,function = "i2c1";
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};
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nand_pins: nand-pins {
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marvell,pins = "mpp0", "mpp1", "mpp2",
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"mpp3", "mpp4", "mpp5",
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"mpp6", "mpp7", "mpp8",
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"mpp9", "mpp10", "mpp11",
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"mpp12", "mpp13";
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marvell,function = "nand";
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};
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sdio_pins: sdio-pins {
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marvell,pins = "mpp24", "mpp25", "mpp26",
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"mpp27", "mpp28", "mpp29";
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marvell,function = "sd";
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};
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spi0_pins: spi0-pins {
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marvell,pins = "mpp0", "mpp1", "mpp4",
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"mpp5", "mpp8", "mpp9";
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marvell,function = "spi0";
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};
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio2: gpio@18180 {
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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};
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systemc: system-controller@18200 {
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compatible = "marvell,armada-375-system-controller";
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reg = <0x18200 0x100>;
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#reset-cells = <2>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-375-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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usbcluster: usb-cluster@18400 {
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compatible = "marvell,armada-375-usb-cluster";
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reg = <0x18400 0x4>;
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#phy-cells = <1>;
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};
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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mpic: interrupt-controller@20a00 {
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compatible = "marvell,mpic";
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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#interrupt-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer@20300 {
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compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<&mpic 5>,
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<&mpic 6>;
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clocks = <&coreclk 0>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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watchdog@20300 {
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compatible = "marvell,armada-375-wdt";
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reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
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clocks = <&coreclk 0>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x10>;
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};
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coherency-fabric@21010 {
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compatible = "marvell,armada-375-coherency-fabric";
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reg = <0x21010 0x1c>;
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};
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usb@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x500>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gateclk 18>;
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phys = <&usbcluster PHY_TYPE_USB2>;
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phy-names = "usb";
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status = "disabled";
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};
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usb@54000 {
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compatible = "marvell,orion-ehci";
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reg = <0x54000 0x500>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gateclk 26>;
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status = "disabled";
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};
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usb3@58000 {
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compatible = "marvell,armada-375-xhci";
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reg = <0x58000 0x20000>,<0x5b880 0x80>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gateclk 16>;
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phys = <&usbcluster PHY_TYPE_USB3>;
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phy-names = "usb";
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status = "disabled";
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};
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|
|
|
xor@60800 {
|
|
compatible = "marvell,orion-xor";
|
|
reg = <0x60800 0x100
|
|
0x60A00 0x100>;
|
|
clocks = <&gateclk 22>;
|
|
status = "okay";
|
|
|
|
xor00 {
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
xor01 {
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
dmacap,memset;
|
|
};
|
|
};
|
|
|
|
xor@60900 {
|
|
compatible = "marvell,orion-xor";
|
|
reg = <0x60900 0x100
|
|
0x60b00 0x100>;
|
|
clocks = <&gateclk 23>;
|
|
status = "okay";
|
|
|
|
xor10 {
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
};
|
|
xor11 {
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmacap,memcpy;
|
|
dmacap,xor;
|
|
dmacap,memset;
|
|
};
|
|
};
|
|
|
|
crypto@90000 {
|
|
compatible = "marvell,armada-375-crypto";
|
|
reg = <0x90000 0x10000>;
|
|
reg-names = "regs";
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 30>, <&gateclk 31>,
|
|
<&gateclk 28>, <&gateclk 29>;
|
|
clock-names = "cesa0", "cesa1",
|
|
"cesaz0", "cesaz1";
|
|
marvell,crypto-srams = <&crypto_sram0>,
|
|
<&crypto_sram1>;
|
|
marvell,crypto-sram-size = <0x800>;
|
|
};
|
|
|
|
sata@a0000 {
|
|
compatible = "marvell,orion-sata";
|
|
reg = <0xa0000 0x5000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 14>, <&gateclk 20>;
|
|
clock-names = "0", "1";
|
|
status = "disabled";
|
|
};
|
|
|
|
nand@d0000 {
|
|
compatible = "marvell,armada370-nand";
|
|
reg = <0xd0000 0x54>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mvsdio@d4000 {
|
|
compatible = "marvell,orion-sdio";
|
|
reg = <0xd4000 0x200>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 17>;
|
|
bus-width = <4>;
|
|
cap-sdio-irq;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
status = "disabled";
|
|
};
|
|
|
|
thermal@e8078 {
|
|
compatible = "marvell,armada375-thermal";
|
|
reg = <0xe8078 0x4>, <0xe807c 0x8>;
|
|
status = "okay";
|
|
};
|
|
|
|
coreclk: mvebu-sar@e8204 {
|
|
compatible = "marvell,armada-375-core-clock";
|
|
reg = <0xe8204 0x04>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
coredivclk: corediv-clock@e8250 {
|
|
compatible = "marvell,armada-375-corediv-clock";
|
|
reg = <0xe8250 0xc>;
|
|
#clock-cells = <1>;
|
|
clocks = <&mainpll>;
|
|
clock-output-names = "nand";
|
|
};
|
|
};
|
|
|
|
pciec: pcie@82000000 {
|
|
compatible = "marvell,armada-370-pcie";
|
|
status = "disabled";
|
|
device_type = "pci";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
|
|
msi-parent = <&mpic>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
ranges =
|
|
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
|
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
|
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
|
|
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
|
|
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
|
|
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
|
|
|
|
pcie0: pcie@1,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
|
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 5>;
|
|
resets = <&systemc 0 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie@2,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
|
reg = <0x1000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
|
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
|
bus-range = <0x00 0xff>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <1>;
|
|
clocks = <&gateclk 6>;
|
|
resets = <&systemc 0 1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
|
|
crypto_sram0: sa-sram0 {
|
|
compatible = "mmio-sram";
|
|
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
|
|
clocks = <&gateclk 30>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
|
|
};
|
|
|
|
crypto_sram1: sa-sram1 {
|
|
compatible = "mmio-sram";
|
|
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
|
|
clocks = <&gateclk 31>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
|
|
};
|
|
};
|
|
};
|