mirror of
https://github.com/AsahiLinux/u-boot
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22a5a9724b
Sync the devicetree with linux-next tag: next-20230525 Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
126 lines
3.7 KiB
Text
126 lines
3.7 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include "rk3588s.dtsi"
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#include "rk3588-pinctrl.dtsi"
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/ {
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i2s8_8ch: i2s@fddc8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddc8000 0x0 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 22>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO0>;
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resets = <&cru SRST_M_I2S8_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s6_8ch: i2s@fddf4000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf4000 0x0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 4>;
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dma-names = "tx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S6_8CH_TX>;
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reset-names = "tx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s7_8ch: i2s@fddf8000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfddf8000 0x0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 21>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S7_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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i2s10_8ch: i2s@fde00000 {
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compatible = "rockchip,rk3588-i2s-tdm";
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reg = <0x0 0xfde00000 0x0 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
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clock-names = "mclk_tx", "mclk_rx", "hclk";
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assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
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assigned-clock-parents = <&cru PLL_AUPLL>;
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dmas = <&dmac2 24>;
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dma-names = "rx";
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power-domains = <&power RK3588_PD_VO1>;
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resets = <&cru SRST_M_I2S10_8CH_RX>;
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reset-names = "rx-m";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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gmac0: ethernet@fe1b0000 {
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compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
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reg = <0x0 0xfe1b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
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<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "macirq", "eth_wake_irq";
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clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
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<&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
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<&cru CLK_GMAC0_PTP_REF>;
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clock-names = "stmmaceth", "clk_mac_ref",
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"pclk_mac", "aclk_mac",
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"ptp_ref";
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power-domains = <&power RK3588_PD_GMAC>;
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resets = <&cru SRST_A_GMAC0>;
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reset-names = "stmmaceth";
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rockchip,grf = <&sys_grf>;
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rockchip,php-grf = <&php_grf>;
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snps,axi-config = <&gmac0_stmmac_axi_setup>;
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snps,mixed-burst;
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snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
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snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
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snps,tso;
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status = "disabled";
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mdio0: mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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};
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gmac0_stmmac_axi_setup: stmmac-axi-config {
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snps,blen = <0 0 0 0 16 8 4>;
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snps,wr_osr_lmt = <4>;
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snps,rd_osr_lmt = <8>;
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};
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gmac0_mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <2>;
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queue0 {};
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queue1 {};
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};
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gmac0_mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <2>;
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queue0 {};
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queue1 {};
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};
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};
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};
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