mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
2fbb8462b0
As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.
To sum up, the autoboot behaves as follows:
[1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
autoboot with no delay, but you can abort it by key input
[2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
autoboot with no delay, with no check for abort
[3] CONFIG_BOOTDELAY=-1
disable autoboot
[4] CONFIG_BOOTDELAY=-2
autoboot with no delay, with no check for abort
As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK. We can control all the
cases only by CONFIG_BOOTDELAY, like this:
[1] CONFIG_BOOTDELAY=0
autoboot with no delay, but you can abort it by key input
[2] CONFIG_BOOTDELAY=-1
disable autoboot
[3] CONFIG_BOOTDELAY=-2
autoboot with no delay, with no check for abort
This commit converts the logic as follow:
CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
--> CONFIG_BOOTDELAY=-2
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicronenergy.com>
Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
181 lines
5.3 KiB
C
181 lines
5.3 KiB
C
/*
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* (C) Copyright 2008
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* Based on include/configs/yosemite.h
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* (C) Copyright 2005-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_440GR 1 /* Specific PPC440GR support */
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#define CONFIG_HOSTNAME gdppc440etx
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#define CONFIG_440 1 /* ... PPC440 family */
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#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
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#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
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#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
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#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
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/*Don't change either of these*/
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#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */
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/*Don't change either of these*/
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#define CONFIG_SYS_USB_DEVICE 0x50000000
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#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
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/*
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* Initial RAM & stack pointer (placed in SDRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
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- GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 2 /* Use UART1 */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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/*
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* Environment
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* Define here the location of the environment variables (FLASH or EEPROM).
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* Note: DENX encourages to use redundant environment in FLASH.
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/
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/*
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* FLASH related
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*/
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif /* CONFIG_ENV_IS_IN_FLASH */
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/*
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* DDR SDRAM
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*/
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#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/
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#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
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#define CONFIG_SYS_SDRAM_BANKS (2)
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#define CONFIG_SDRAM_BANK0
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#define CONFIG_SDRAM_BANK1
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#define CONFIG_SYS_SDRAM0_TR0 0x410a4012
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#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000
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#define CONFIG_SYS_SDRAM0_RTR 0x04080000
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#define CONFIG_SYS_SDRAM0_CFG0 0x80000000
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#undef CONFIG_SDRAM_ECC
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc180000\0" \
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""
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY_ADDR 1
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#define CONFIG_PHY1_ADDR 3
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#ifdef DEBUG
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#define CONFIG_PANIC_HANG
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#endif
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_PCI
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#undef CONFIG_CMD_EEPROM
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/*
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* PCI stuff
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/
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#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \
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CONFIG_SYS_PCI_MEMBASE*/
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/* Board-specific PCI */
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#define CONFIG_SYS_PCI_TARGET_INIT
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#define CONFIG_SYS_PCI_MASTER_INIT
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CONFIG_SYS_EBC_PB0AP 0x03017200
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#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
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#endif /* __CONFIG_H */
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