mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
61e745d131
The maximum supported peripheral clock frequency of the zynq depends on the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz respectively 25 MHz. Use the max-frequency value of the device tree to determine the maximal supported peripheral clock frequency. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
114 lines
2.5 KiB
C
114 lines
2.5 KiB
C
/*
|
|
* (C) Copyright 2013 - 2015 Xilinx, Inc.
|
|
*
|
|
* Xilinx Zynq SD Host Controller Interface
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <clk.h>
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <fdtdec.h>
|
|
#include <libfdt.h>
|
|
#include <malloc.h>
|
|
#include <sdhci.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#ifndef CONFIG_ZYNQ_SDHCI_MIN_FREQ
|
|
# define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0
|
|
#endif
|
|
|
|
struct arasan_sdhci_plat {
|
|
struct mmc_config cfg;
|
|
struct mmc mmc;
|
|
unsigned int f_max;
|
|
};
|
|
|
|
static int arasan_sdhci_probe(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct sdhci_host *host = dev_get_priv(dev);
|
|
struct clk clk;
|
|
unsigned long clock;
|
|
int ret;
|
|
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get clock\n");
|
|
return ret;
|
|
}
|
|
|
|
clock = clk_get_rate(&clk);
|
|
if (IS_ERR_VALUE(clock)) {
|
|
dev_err(dev, "failed to get rate\n");
|
|
return clock;
|
|
}
|
|
debug("%s: CLK %ld\n", __func__, clock);
|
|
|
|
ret = clk_enable(&clk);
|
|
if (ret && ret != -ENOSYS) {
|
|
dev_err(dev, "failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
|
|
SDHCI_QUIRK_BROKEN_R1B;
|
|
|
|
#ifdef CONFIG_ZYNQ_HISPD_BROKEN
|
|
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
|
|
#endif
|
|
|
|
host->max_clk = clock;
|
|
|
|
ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
|
|
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
|
|
host->mmc = &plat->mmc;
|
|
if (ret)
|
|
return ret;
|
|
host->mmc->priv = host;
|
|
host->mmc->dev = dev;
|
|
upriv->mmc = host->mmc;
|
|
|
|
return sdhci_probe(dev);
|
|
}
|
|
|
|
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
|
|
struct sdhci_host *host = dev_get_priv(dev);
|
|
|
|
host->name = dev->name;
|
|
host->ioaddr = (void *)dev_get_addr(dev);
|
|
|
|
plat->f_max = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
|
|
"max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int arasan_sdhci_bind(struct udevice *dev)
|
|
{
|
|
struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
|
|
|
|
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
static const struct udevice_id arasan_sdhci_ids[] = {
|
|
{ .compatible = "arasan,sdhci-8.9a" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(arasan_sdhci_drv) = {
|
|
.name = "arasan_sdhci",
|
|
.id = UCLASS_MMC,
|
|
.of_match = arasan_sdhci_ids,
|
|
.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
|
|
.ops = &sdhci_ops,
|
|
.bind = arasan_sdhci_bind,
|
|
.probe = arasan_sdhci_probe,
|
|
.priv_auto_alloc_size = sizeof(struct sdhci_host),
|
|
.platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
|
|
};
|