u-boot/arch/arm/dts/bitmain-antminer-s9.dts
Michal Simek 1332a781e1 ARM: zynq: Add partition description
Xilinx is using standard mtd partition layout for quite a long time. It is
used for testing purpose on evaluation boards.
Also #address/size-cells shouldn't be present without nodes which should
use them that's why move them from zynq-7000.dtsi to nand/nor nodes
directly.

The patch was tested on zc706 and zedboard(with also increasing max
frequency and rx bus width).

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4c3348981bba32d3892194420d78fe8621c47534.1698837725.git.michal.simek@amd.com
2023-11-07 13:47:09 +01:00

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// SPDX-License-Identifier: GPL-2.0
/*
* Bitmain Antminer S9 board DTS
*
* Copyright (C) 2018 Michal Simek
* Copyright (C) 2018 VanguardiaSur
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
model = "Bitmain Antminer S9 Board";
compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
mmc0 = &sdhci0;
gpio0 = &gpio0;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
bootcount@efffff0 {
reg = <0xefffff0 0x10>;
no-map;
};
fpga_space@f000000 {
reg = <0xf000000 0x1000000>;
no-map;
};
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&nfc0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
nand@0 {
reg = <0>;
};
};
&smcc {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
/* 0362/5e62 */
ethernet_phy: ethernet-phy@1 {
reg = <1>;
};
};
&sdhci0 {
bootph-all;
status = "okay";
disable-wp;
};
&uart1 {
bootph-all;
status = "okay";
};
&watchdog0 {
reset-on-timeout;
timeout-sec = <200>;
};