mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-10-21 13:35:09 +00:00
dcfd37e5ef
The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
21 lines
530 B
C
21 lines
530 B
C
/*
|
|
* Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _LPC32XX_SYS_PROTO_H
|
|
#define _LPC32XX_SYS_PROTO_H
|
|
|
|
#include <asm/arch/emc.h>
|
|
|
|
void lpc32xx_uart_init(unsigned int uart_id);
|
|
void lpc32xx_mac_init(void);
|
|
void lpc32xx_mlc_nand_init(void);
|
|
void lpc32xx_slc_nand_init(void);
|
|
void lpc32xx_i2c_init(unsigned int devnum);
|
|
void lpc32xx_ssp_init(void);
|
|
#if defined(CONFIG_SPL_BUILD)
|
|
void ddr_init(const struct emc_dram_settings *dram);
|
|
#endif
|
|
#endif /* _LPC32XX_SYS_PROTO_H */
|