mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 21:54:01 +00:00
65abdd1978
Rename rmobile.h to renesas.h because all the chips are made
by Renesas, while only a subset of them is from the R-Mobile
line.
Use the following command to perform the rename:
"
$ git grep -l 'include.*rmobile.h' | \
xargs -I {} sed -i '/include.*rmobile.h/ s@rmobile.h@renesas.h@g' {}
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/hoperun/hihope-rzg2/hihope-rzg2.c
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* This file is HiHope RZ/G2[HMN] board support.
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*
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* Copyright (C) 2021 Renesas Electronics Corporation
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/renesas.h>
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#include <asm/arch/rcar-mstp.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#define RST_BASE 0xE6160000
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#define RST_CA57RESCNT (RST_BASE + 0x40)
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#define RST_CA53RESCNT (RST_BASE + 0x44)
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#define RST_CA57_CODE 0xA5A5000F
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#define RST_CA53_CODE 0x5A5A000F
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DECLARE_GLOBAL_DATA_PTR;
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#define HSUSB_MSTP704 BIT(4) /* HSUSB */
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/* HSUSB block registers */
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#define HSUSB_REG_LPSTS 0xE6590102
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#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
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#define HSUSB_REG_UGCTRL2 0xE6590184
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#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
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#define HSUSB_REG_UGCTRL2_RESERVED_3 0x1 /* bit[3:0] should be B'0001 */
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#define PRR_REGISTER (0xFFF00044)
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int board_init(void)
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{
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u32 i;
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
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/* Configure the HSUSB block */
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mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
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/*
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* We need to add a barrier instruction after HSUSB module stop release.
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* This barrier instruction can be either reading back the same MSTP
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* register or any other register in the same IP block. So like linux
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* adding check for MSTPSR register, which indicates the clock has been
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* started.
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*/
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for (i = 1000; i > 0; --i) {
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if (!(readl(MSTPSR7) & HSUSB_MSTP704))
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break;
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cpu_relax();
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}
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/* Select EHCI/OHCI host module for USB2.0 ch0 */
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writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
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HSUSB_REG_UGCTRL2);
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/* low power status */
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setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
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return 0;
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}
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void reset_cpu(void)
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{
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unsigned long midr, cputype;
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asm volatile("mrs %0, midr_el1" : "=r" (midr));
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cputype = (midr >> 4) & 0xfff;
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if (cputype == 0xd03)
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writel(RST_CA53_CODE, RST_CA53RESCNT);
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else
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writel(RST_CA57_CODE, RST_CA57RESCNT);
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}
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#if defined(CONFIG_MULTI_DTB_FIT)
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/* If the firmware passed a device tree, use it for board identification. */
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extern u64 rcar_atf_boot_args[];
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static bool is_hoperun_hihope_rzg2_board(const char *board_name)
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{
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void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
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bool ret = false;
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if ((fdt_magic(atf_fdt_blob) == FDT_MAGIC) &&
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(fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0))
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ret = true;
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return ret;
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}
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int board_fit_config_name_match(const char *name)
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{
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if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
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!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
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return 0;
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if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2n") &&
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!strcmp(name, "r8a774b1-hihope-rzg2n-u-boot"))
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return 0;
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if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2h") &&
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!strcmp(name, "r8a774e1-hihope-rzg2h-u-boot"))
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return 0;
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return -1;
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}
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#endif
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