Thor Thayer 8097aee3ab ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access ... The ECC registers in the SDRAM HMC Adapter should always be accessible (both when ECC is enabled and disabled). Currently, the registers are accessible only when ECC is enabled. The ECC Enabled bit is used to determine the status of ECC by later OSes so always allow access. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>		2020-01-07 14:38:34 +01:00
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Kconfig	ddr: altera: agilex: Add SDRAM driver for Agilex	2020-01-07 14:38:33 +01:00
Makefile	ddr: altera: agilex: Add SDRAM driver for Agilex	2020-01-07 14:38:33 +01:00
sdram_agilex.c	ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access	2020-01-07 14:38:34 +01:00
sdram_arria10.c	common: Move some cache and MMU functions out of common.h	2019-12-02 18:23:55 -05:00
sdram_gen5.c	arm: socfpga: Convert system manager from struct to defines	2020-01-07 14:38:33 +01:00
sdram_s10.c	ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC Access	2020-01-07 14:38:34 +01:00
sdram_s10.h	ddr: altera: Restructure Stratix 10 SDRAM driver	2020-01-07 14:38:33 +01:00
sdram_soc64.c	ddr: altera: agilex: Add SDRAM driver for Agilex	2020-01-07 14:38:33 +01:00
sdram_soc64.h	ddr: altera: agilex: Add SDRAM driver for Agilex	2020-01-07 14:38:33 +01:00
sequencer.c	dm: ddr: socfpga: fix gen5 ddr driver to not use bss	2019-07-21 12:45:01 +02:00
sequencer.h	dm: ddr: socfpga: fix gen5 ddr driver to not use bss	2019-07-21 12:45:01 +02:00