u-boot/arch/arm/mach-socfpga/Kconfig
Marek Vasut 934aec71d6 ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 22:35:42 +02:00

144 lines
4.2 KiB
Text

if ARCH_SOCFPGA
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_ARRIA10
bool
select ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
select CLK
select SPL_CLK if SPL
select DM_I2C
select DM_RESET
select SPL_DM_RESET if SPL
select REGMAP
select SPL_REGMAP if SPL
select SYSCON
select SPL_SYSCON if SPL
select ETH_DESIGNWARE_SOCFPGA
config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_GEN5
bool
select ALTERA_SDRAM
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
select ARMV8_SPIN_TABLE
choice
prompt "Altera SOCFPGA board select"
optional
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
bool "Devboards DBM-SoC1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_IS1
bool "IS1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
bool "samtec VIN|ING FPGA (Cyclone V)"
select BOARD_LATE_INIT
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_STRATIX10_SOCDK
bool "Intel SOCFPGA SoCDK (Stratix 10)"
select TARGET_SOCFPGA_STRATIX10
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_DE10_NANO
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
endchoice
config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "sr1500" if TARGET_SOCFPGA_SR1500
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif