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https://github.com/AsahiLinux/u-boot
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6786ce1ce1
Perform a simple rename of CONFIG_STACKBASE to CFG_STACKBASE Signed-off-by: Tom Rini <trini@konsulko.com>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA_COMMON_H_
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#define _TEGRA_COMMON_H_
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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/*
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* High Level Configuration Options
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*/
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#include <asm/arch/tegra.h> /* get chip and board defs */
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/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
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#ifndef CONFIG_ARM64
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#define CFG_SYS_TIMER_RATE 1000000
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#define CFG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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#endif
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/* Environment */
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/*
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* NS16550 Configuration
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*/
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#define CFG_SYS_NS16550_CLK V_NS16550_CLK
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#ifdef CONFIG_ARM64
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#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb"
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#else
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#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb"
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
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#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CFG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
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#ifndef CONFIG_ARM64
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#define CFG_SYS_INIT_RAM_ADDR CFG_STACKBASE
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#define CFG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
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/* Defines for SPL */
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#endif
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#endif /* _TEGRA_COMMON_H_ */
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