mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
da962b7175
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fa.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
225 lines
6.4 KiB
C
225 lines
6.4 KiB
C
/*
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* (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __MXC_NAND_H
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#define __MXC_NAND_H
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/*
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* Register map and bit definitions for the Freescale NAND Flash Controller
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* present in various i.MX devices.
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*
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* MX31 and MX27 have version 1, which has:
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* 4 512-byte main buffers and
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* 4 16-byte spare buffers
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* to support up to 2K byte pagesize nand.
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* Reading or writing a 2K page requires 4 FDI/FDO cycles.
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*
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* MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
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* have:
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* 8 512-byte main buffers and
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* 8 64-byte spare buffers
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* to support up to 4K byte pagesize nand.
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* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
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* Also some of registers are moved and/or changed meaning as seen below.
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*/
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#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
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#define MXC_NFC_V1
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#define is_mxc_nfc_1() 1
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#define is_mxc_nfc_21() 0
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#define is_mxc_nfc_32() 0
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#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
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#define MXC_NFC_V2_1
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#define is_mxc_nfc_1() 0
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#define is_mxc_nfc_21() 1
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#define is_mxc_nfc_32() 0
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#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
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#define MXC_NFC_V3
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#define MXC_NFC_V3_2
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#define is_mxc_nfc_1() 0
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#define is_mxc_nfc_21() 0
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#define is_mxc_nfc_32() 1
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#else
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#error "MXC NFC implementation not supported"
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#endif
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#define is_mxc_nfc_3() is_mxc_nfc_32()
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#if defined(MXC_NFC_V1)
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#define NAND_MXC_NR_BUFS 4
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#define NAND_MXC_SPARE_BUF_SIZE 16
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#define NAND_MXC_REG_OFFSET 0xe00
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#define NAND_MXC_2K_MULTI_CYCLE
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#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
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#define NAND_MXC_NR_BUFS 8
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#define NAND_MXC_SPARE_BUF_SIZE 64
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#define NAND_MXC_REG_OFFSET 0x1e00
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#endif
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struct mxc_nand_regs {
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u8 main_area[NAND_MXC_NR_BUFS][0x200];
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u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
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/*
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* reserved size is offset of nfc registers
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* minus total main and spare sizes
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*/
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u8 reserved1[NAND_MXC_REG_OFFSET
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- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
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#if defined(MXC_NFC_V1)
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u16 buf_size;
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u16 reserved2;
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u16 buf_addr;
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u16 flash_addr;
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u16 flash_cmd;
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u16 config;
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u16 ecc_status_result;
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u16 rsltmain_area;
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u16 rsltspare_area;
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u16 wrprot;
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u16 unlockstart_blkaddr;
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u16 unlockend_blkaddr;
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u16 nf_wrprst;
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u16 config1;
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u16 config2;
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#elif defined(MXC_NFC_V2_1)
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u16 reserved2[2];
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u16 buf_addr;
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u16 flash_addr;
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u16 flash_cmd;
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u16 config;
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u32 ecc_status_result;
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u16 spare_area_size;
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u16 wrprot;
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u16 reserved3[2];
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u16 nf_wrprst;
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u16 config1;
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u16 config2;
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u16 reserved4;
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u16 unlockstart_blkaddr;
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u16 unlockend_blkaddr;
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u16 unlockstart_blkaddr1;
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u16 unlockend_blkaddr1;
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u16 unlockstart_blkaddr2;
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u16 unlockend_blkaddr2;
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u16 unlockstart_blkaddr3;
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u16 unlockend_blkaddr3;
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#elif defined(MXC_NFC_V3_2)
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u32 flash_cmd;
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u32 flash_addr[12];
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u32 config1;
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u32 ecc_status_result;
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u32 status_sum;
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u32 launch;
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#endif
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};
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#ifdef MXC_NFC_V3_2
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struct mxc_nand_ip_regs {
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u32 wrprot;
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u32 wrprot_unlock_blkaddr[8];
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u32 config2;
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u32 config3;
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u32 ipc;
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u32 err_addr;
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u32 delay_line;
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};
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#endif
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/* Set FCMD to 1, rest to 0 for Command operation */
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#define NFC_CMD 0x1
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/* Set FADD to 1, rest to 0 for Address operation */
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#define NFC_ADDR 0x2
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/* Set FDI to 1, rest to 0 for Input operation */
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#define NFC_INPUT 0x4
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/* Set FDO to 001, rest to 0 for Data Output operation */
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#define NFC_OUTPUT 0x8
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/* Set FDO to 010, rest to 0 for Read ID operation */
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#define NFC_ID 0x10
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/* Set FDO to 100, rest to 0 for Read Status operation */
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#define NFC_STATUS 0x20
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#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
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#define NFC_CONFIG1_SP_EN (1 << 2)
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#define NFC_CONFIG1_RST (1 << 6)
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#define NFC_CONFIG1_CE (1 << 7)
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#elif defined(MXC_NFC_V3_2)
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#define NFC_CONFIG1_SP_EN (1 << 0)
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#define NFC_CONFIG1_CE (1 << 1)
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#define NFC_CONFIG1_RST (1 << 2)
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#endif
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#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
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#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
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#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
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#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
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#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
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#define NFC_V2_CONFIG1_FP_INT (1 << 11)
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#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
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#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
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#define NFC_V1_V2_CONFIG2_INT (1 << 15)
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#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
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#define NFC_V3_CONFIG2_PS_512 (0 << 0)
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#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
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#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
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#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
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#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
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#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
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#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
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#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
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#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
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#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
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#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
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#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
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#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
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#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
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#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
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#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
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#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
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#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
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#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
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#define NFC_V3_CONFIG3_FW8 (1 << 3)
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#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
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#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
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#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
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#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
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#define NFC_V3_WRPROT_UNLOCK (1 << 2)
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#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
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#define NFC_V3_IPC_CREQ (1 << 0)
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#define NFC_V3_IPC_INT (1 << 31)
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#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
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#define operation config2
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#define readnfc readw
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#define writenfc writew
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#elif defined(MXC_NFC_V3_2)
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#define operation launch
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#define readnfc readl
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#define writenfc writel
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#endif
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#endif /* __MXC_NAND_H */
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