u-boot/arch/powerpc/cpu/mpc8xxx
York Sun 57495e4e5e powerpc/mpc8xxx: Update DDR registers
DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
	000 -> Termsel off
	001 -> 120 Ohm
	010 -> 180 Ohm
	011 -> 75 Ohm
	100 -> 110 Ohm
	101 -> 60 Ohm
	110 -> 70 Ohm
	111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-22 14:31:26 -05:00
..
ddr powerpc/mpc8xxx: Update DDR registers 2012-10-22 14:31:26 -05:00
cpu.c powerpc/mpc85xx: Add B4860 and variant SoCs 2012-10-22 14:31:24 -05:00
fdt.c powerpc/mpc8xxx: Fix USB device-tree fixup 2012-10-22 14:31:12 -05:00
fsl_ifc.c Added new ext fields to IFC 2012-08-23 12:16:55 -05:00
fsl_lbc.c fsl_lbc: add printout of LCRR and LBCR to local bus regs 2012-01-13 12:56:06 -06:00
Makefile powerpc/85xx: Add support for Integrated Flash Controller (IFC) 2011-04-04 09:24:40 -05:00
srio.c powerpc/mpc85xx: Add T4240 SoC 2012-10-22 14:31:23 -05:00