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6d16157426
This imports some defines for esr and spsr from Linux v5.16. I have modified the includes and fixed some indentation nits but otherwise it is the same. There are a lot more defines than we need, but it doesn't hurt. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
206 lines
4.9 KiB
C
206 lines
4.9 KiB
C
/*
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* linux/include/asm-arm/proc-armv/ptrace.h
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*
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* Copyright (C) 1996-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROC_PTRACE_H
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#define __ASM_PROC_PTRACE_H
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#ifdef CONFIG_ARM64
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#define PCMASK 0
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/*
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* PSR bits
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*/
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#define PSR_MODE_EL0t 0x00000000
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#define PSR_MODE_EL1t 0x00000004
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#define PSR_MODE_EL1h 0x00000005
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#define PSR_MODE_EL2t 0x00000008
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#define PSR_MODE_EL2h 0x00000009
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#define PSR_MODE_EL3t 0x0000000c
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#define PSR_MODE_EL3h 0x0000000d
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#define PSR_MODE_MASK 0x0000000f
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/* AArch32 CPSR bits */
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#define PSR_MODE32_BIT 0x00000010
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/* AArch64 SPSR bits */
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#define PSR_F_BIT 0x00000040
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#define PSR_I_BIT 0x00000080
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#define PSR_A_BIT 0x00000100
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#define PSR_D_BIT 0x00000200
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#define PSR_BTYPE_MASK 0x00000c00
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#define PSR_SSBS_BIT 0x00001000
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#define PSR_PAN_BIT 0x00400000
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#define PSR_UAO_BIT 0x00800000
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#define PSR_DIT_BIT 0x01000000
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#define PSR_TCO_BIT 0x02000000
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#define PSR_V_BIT 0x10000000
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#define PSR_C_BIT 0x20000000
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#define PSR_Z_BIT 0x40000000
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#define PSR_N_BIT 0x80000000
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#define PSR_BTYPE_SHIFT 10
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/*
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* Groups of PSR bits
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*/
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#define PSR_f 0xff000000 /* Flags */
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#define PSR_s 0x00ff0000 /* Status */
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#define PSR_x 0x0000ff00 /* Extension */
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#define PSR_c 0x000000ff /* Control */
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/* Convenience names for the values of PSTATE.BTYPE */
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#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
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#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
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/* SPSR_ELx bits for exceptions taken from AArch32 */
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#define PSR_AA32_MODE_MASK 0x0000001f
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#define PSR_AA32_MODE_USR 0x00000010
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#define PSR_AA32_MODE_FIQ 0x00000011
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#define PSR_AA32_MODE_IRQ 0x00000012
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#define PSR_AA32_MODE_SVC 0x00000013
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#define PSR_AA32_MODE_ABT 0x00000017
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#define PSR_AA32_MODE_HYP 0x0000001a
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#define PSR_AA32_MODE_UND 0x0000001b
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#define PSR_AA32_MODE_SYS 0x0000001f
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#define PSR_AA32_T_BIT 0x00000020
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#define PSR_AA32_F_BIT 0x00000040
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#define PSR_AA32_I_BIT 0x00000080
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#define PSR_AA32_A_BIT 0x00000100
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#define PSR_AA32_E_BIT 0x00000200
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#define PSR_AA32_PAN_BIT 0x00400000
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#define PSR_AA32_SSBS_BIT 0x00800000
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#define PSR_AA32_DIT_BIT 0x01000000
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#define PSR_AA32_Q_BIT 0x08000000
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#define PSR_AA32_V_BIT 0x10000000
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#define PSR_AA32_C_BIT 0x20000000
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#define PSR_AA32_Z_BIT 0x40000000
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#define PSR_AA32_N_BIT 0x80000000
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#define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */
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#define PSR_AA32_GE_MASK 0x000f0000
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#ifndef __ASSEMBLY__
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/*
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* This struct defines the way the registers are stored
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* on the stack during an exception.
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*/
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struct pt_regs {
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unsigned long spsr;
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unsigned long elr;
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unsigned long esr;
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unsigned long regs[31];
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};
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_ARM64 */
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#define USR26_MODE 0x00
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#define FIQ26_MODE 0x01
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#define IRQ26_MODE 0x02
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#define SVC26_MODE 0x03
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#define USR_MODE 0x10
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#define FIQ_MODE 0x11
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#define IRQ_MODE 0x12
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#define SVC_MODE 0x13
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#define MON_MODE 0x16
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#define ABT_MODE 0x17
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#define HYP_MODE 0x1a
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#define UND_MODE 0x1b
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#define SYSTEM_MODE 0x1f
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#define MODE_MASK 0x1f
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#define T_BIT 0x20
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#define F_BIT 0x40
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#define I_BIT 0x80
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#define A_BIT 0x100
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#define CC_V_BIT (1 << 28)
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#define CC_C_BIT (1 << 29)
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#define CC_Z_BIT (1 << 30)
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#define CC_N_BIT (1 << 31)
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#define PCMASK 0
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#ifndef __ASSEMBLY__
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/* this struct defines the way the registers are stored on the
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stack during a system call. */
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struct pt_regs {
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long uregs[18];
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};
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#define ARM_cpsr uregs[16]
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#define ARM_pc uregs[15]
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#define ARM_lr uregs[14]
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#define ARM_sp uregs[13]
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#define ARM_ip uregs[12]
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#define ARM_fp uregs[11]
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#define ARM_r10 uregs[10]
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#define ARM_r9 uregs[9]
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#define ARM_r8 uregs[8]
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#define ARM_r7 uregs[7]
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#define ARM_r6 uregs[6]
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#define ARM_r5 uregs[5]
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#define ARM_r4 uregs[4]
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#define ARM_r3 uregs[3]
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#define ARM_r2 uregs[2]
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#define ARM_r1 uregs[1]
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#define ARM_r0 uregs[0]
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#define ARM_ORIG_r0 uregs[17]
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#ifdef __KERNEL__
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#define user_mode(regs) \
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(((regs)->ARM_cpsr & 0xf) == 0)
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#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
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#define thumb_mode(regs) \
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(((regs)->ARM_cpsr & T_BIT))
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#else
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#define thumb_mode(regs) (0)
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#endif
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#define processor_mode(regs) \
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((regs)->ARM_cpsr & MODE_MASK)
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#define interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & I_BIT))
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#define fast_interrupts_enabled(regs) \
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(!((regs)->ARM_cpsr & F_BIT))
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#define condition_codes(regs) \
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((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
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/* Are the current registers suitable for user mode?
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* (used to maintain security in signal handlers)
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*/
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static inline int valid_user_regs(struct pt_regs *regs)
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{
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if ((regs->ARM_cpsr & 0xf) == 0 &&
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(regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
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return 1;
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/*
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* Force CPSR to something logical...
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*/
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regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
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return 0;
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}
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARM64 */
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#endif
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