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https://github.com/AsahiLinux/u-boot
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58eb869ffc
This patch adds the "ecctest" command to test and simulate ECC errors (single bit and/or double bit) while running from SDRAM. Currently only the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT). This is done by copying and calling functions, modifying the SDRAM controller operation mode, in internal SRAM/OCM. For correctable ECC errors (single bit) only the status will be printed since the DDR2 controller doesn't provide the faulting address: => ecctest 1000000 1 Using address 01000000 for 1 bit ECC error injection ECC: Correctable error Uncorrectable ECC errors (double bit) will also display the faulting address: => ecctest 1000000 2 Using address 01000000 for 2 bit ECC error injection ECC: Uncorrectable error at 0x0001000000 To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST in the board config header. Tested on katmai and t3corp. Signed-off-by: Stefan Roese <sr@denx.de>
95 lines
2.2 KiB
Makefile
95 lines
2.2 KiB
Makefile
#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).a
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START := resetvec.o
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START += start.o
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SOBJS := cache.o
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SOBJS += dcr.o
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SOBJS += kgdb.o
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COBJS := 40x_spd_sdram.o
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COBJS += 44x_spd_ddr.o
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COBJS += 44x_spd_ddr2.o
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ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION
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COBJS += 4xx_ibm_ddr2_autocalib.o
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endif
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COBJS += 4xx_pci.o
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COBJS += 4xx_pcie.o
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COBJS += bedbug_405.o
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ifdef CONFIG_CMD_CHIP_CONFIG
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COBJS += cmd_chip_config.o
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endif
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COBJS += commproc.o
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COBJS += cpu.o
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COBJS += cpu_init.o
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COBJS += denali_data_eye.o
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COBJS += denali_spd_ddr2.o
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COBJS += ecc.o
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ifdef CONFIG_CMD_ECCTEST
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COBJS += cmd_ecctest.o
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endif
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COBJS += fdt.o
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COBJS += interrupts.o
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COBJS += iop480_uart.o
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ifdef CONFIG_CMD_REGINFO
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COBJS += reginfo.o
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endif
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COBJS += sdram.o
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COBJS += speed.o
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COBJS += tlb.o
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COBJS += traps.o
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COBJS += usb.o
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COBJS += usb_ohci.o
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COBJS += usbdev.o
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ifndef CONFIG_XILINX_440
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COBJS += 4xx_uart.o
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COBJS += gpio.o
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COBJS += miiphy.o
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COBJS += uic.o
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else
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COBJS += xilinx_irq.o
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endif
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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START := $(addprefix $(obj),$(START))
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all: $(obj).depend $(START) $(LIB)
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$(LIB): $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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