u-boot/arch/arm/dts/ast2500-u-boot.dtsi
Eddie James 30231e0ddb ARM: dts: ast2500: Add SDHCI nodes
Add nodes for the Aspeed SD controllers with their necessary properties.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
2019-09-05 15:27:31 +08:00

88 lines
1.4 KiB
Text

#include <dt-bindings/clock/ast2500-scu.h>
#include <dt-bindings/reset/ast2500-reset.h>
#include "ast2500.dtsi"
/ {
scu: clock-controller@1e6e2000 {
compatible = "aspeed,ast2500-scu";
reg = <0x1e6e2000 0x1000>;
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
};
rst: reset-controller {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
#reset-cells = <1>;
};
sdrammc: sdrammc@1e6e0000 {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
resets = <&rst AST_RESET_SDRAM>;
};
ahb {
u-boot,dm-pre-reloc;
apb {
u-boot,dm-pre-reloc;
sdhci0: sdhci@1e740100 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>;
resets = <&rst AST_RESET_SDIO>;
};
sdhci1: sdhci@1e740200 {
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
clocks = <&scu BCLK_SDCLK>;
resets = <&rst AST_RESET_SDIO>;
};
};
};
};
&uart1 {
clocks = <&scu PCLK_UART1>;
};
&uart2 {
clocks = <&scu PCLK_UART2>;
};
&uart3 {
clocks = <&scu PCLK_UART3>;
};
&uart4 {
clocks = <&scu PCLK_UART4>;
};
&uart5 {
clocks = <&scu PCLK_UART5>;
};
&timer {
u-boot,dm-pre-reloc;
};
&mac0 {
clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
};
&mac1 {
clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
};