mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 06:04:34 +00:00
56db948b85
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
140 lines
3.6 KiB
C
140 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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* Copyright 2015 Freescale Semiconductor
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*/
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#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
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#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#ifdef CONFIG_FSL_LSCH2
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#include <asm/arch/immap_lsch2.h>
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#endif
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#ifdef CONFIG_FSL_LSCH3
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#include <asm/arch/immap_lsch3.h>
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
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#define gur_in32(a) in_le32(a)
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#define gur_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
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#define gur_in32(a) in_be32(a)
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#define gur_out32(a, v) out_be32(a, v)
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#endif
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#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define scfg_in32(a) in_le32(a)
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#define scfg_out32(a, v) out_le32(a, v)
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#define scfg_clrbits32(addr, clear) clrbits_le32(addr, clear)
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#define scfg_clrsetbits32(addr, clear, set) clrsetbits_le32(addr, clear, set)
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#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
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#define scfg_in32(a) in_be32(a)
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#define scfg_out32(a, v) out_be32(a, v)
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#define scfg_clrbits32(addr, clear) clrbits_be32(addr, clear)
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#define scfg_clrsetbits32(addr, clear, set) clrsetbits_be32(addr, clear, set)
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#endif
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#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
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#define pex_lut_in32(a) in_le32(a)
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#define pex_lut_out32(a, v) out_le32(a, v)
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#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
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#define pex_lut_in32(a) in_be32(a)
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#define pex_lut_out32(a, v) out_be32(a, v)
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#endif
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#ifndef __ASSEMBLY__
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struct cpu_type {
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char name[15];
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u32 soc_ver;
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u32 num_cores;
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};
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#define CPU_TYPE_ENTRY(n, v, nc) \
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{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
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#ifdef CONFIG_TFABOOT
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#define SMC_DRAM_BANK_INFO (0xC200FF12)
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#define SIP_SVC_RCW 0xC200FF18
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phys_size_t tfa_get_dram_size(void);
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enum boot_src {
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BOOT_SOURCE_RESERVED = 0,
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BOOT_SOURCE_IFC_NOR,
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BOOT_SOURCE_IFC_NAND,
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BOOT_SOURCE_QSPI_NOR,
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BOOT_SOURCE_QSPI_NAND,
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BOOT_SOURCE_XSPI_NOR,
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BOOT_SOURCE_XSPI_NAND,
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BOOT_SOURCE_SD_MMC,
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BOOT_SOURCE_SD_MMC2,
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BOOT_SOURCE_I2C1_EXTENDED,
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};
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enum boot_src get_boot_src(void);
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#endif
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#endif
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#define SVR_WO_E 0xFFFFFE
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#define SVR_LS1012A 0x870400
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#define SVR_LS1043A 0x879200
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#define SVR_LS1023A 0x879208
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#define SVR_LS1046A 0x870700
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#define SVR_LS1026A 0x870708
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#define SVR_LS1048A 0x870320
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#define SVR_LS1084A 0x870302
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#define SVR_LS1088A 0x870300
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#define SVR_LS1044A 0x870322
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#define SVR_LS2045A 0x870120
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#define SVR_LS2080A 0x870110
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#define SVR_LS2085A 0x870100
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#define SVR_LS2040A 0x870130
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#define SVR_LS2088A 0x870900
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#define SVR_LS2084A 0x870910
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#define SVR_LS2048A 0x870920
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#define SVR_LS2044A 0x870930
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#define SVR_LS2081A 0x870918
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#define SVR_LS2041A 0x870914
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#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
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#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
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#define SVR_REV(svr) (((svr) >> 0) & 0xff)
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#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
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#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
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#define IS_SVR_REV(svr, maj, min) \
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((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
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#define SVR_DEV(svr) ((svr) >> 8)
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#define IS_SVR_DEV(svr, dev) (((svr) >> 16) == (dev))
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_FSL_LSCH3
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void fsl_lsch3_early_init_f(void);
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int get_core_volt_from_fuse(void);
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#elif defined(CONFIG_FSL_LSCH2)
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void fsl_lsch2_early_init_f(void);
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int setup_chip_volt(void);
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/* Setup core vdd in unit mV */
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int board_setup_core_volt(u32 vdd);
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#ifdef CONFIG_FSL_PFE
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void init_pfe_scfg_dcfg_regs(void);
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#endif
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#endif
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#ifdef CONFIG_QSPI_AHB_INIT
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int qspi_ahb_init(void);
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#endif
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void cpu_name(char *name);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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void erratum_a009635(void);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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void erratum_a010315(void);
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#endif
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bool soc_has_dp_ddr(void);
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bool soc_has_aiop(void);
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#endif
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#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
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