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56c3aa9ab9
The QEMU emulation of m68k does not support DMA timer, the only timer that is supported is the PIT timer. Implement trivial PIT timer support for m68k. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
355 lines
11 KiB
C
355 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* ColdFire Internal Memory Map and Defines
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*
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* Copyright 2004-2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __IMMAP_H
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#define __IMMAP_H
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#if defined(CONFIG_MCF520x)
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#include <asm/immap_520x.h>
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#include <asm/m520x.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
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#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (6)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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#endif /* CONFIG_M520x */
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#ifdef CONFIG_M5235
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#include <asm/immap_5235.h>
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#include <asm/m5235.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
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#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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#endif /* CONFIG_M5235 */
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#ifdef CONFIG_M5249
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#include <asm/immap_5249.h>
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#include <asm/m5249.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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#define CFG_SYS_INTR_BASE (MMAP_INTC)
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#define CFG_SYS_NUM_IRQS (64)
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
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#define CFG_SYS_TMRINTR_NO (31)
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#define CFG_SYS_TMRINTR_MASK (0x00000400)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#endif /* CONFIG_M5249 */
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#ifdef CONFIG_M5253
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#include <asm/immap_5253.h>
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#include <asm/m5249.h>
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#include <asm/m5253.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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#define CFG_SYS_INTR_BASE (MMAP_INTC)
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#define CFG_SYS_NUM_IRQS (64)
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
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#define CFG_SYS_TMRINTR_NO (27)
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#define CFG_SYS_TMRINTR_MASK (0x00000400)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#endif /* CONFIG_M5253 */
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#ifdef CONFIG_M5271
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#include <asm/immap_5271.h>
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#include <asm/m5271.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
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#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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#endif /* CONFIG_M5271 */
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#ifdef CONFIG_M5272
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#include <asm/immap_5272.h>
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#include <asm/m5272.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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#define CFG_SYS_INTR_BASE (MMAP_INTC)
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#define CFG_SYS_NUM_IRQS (64)
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_TMR0)
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#define CFG_SYS_TMR_BASE (MMAP_TMR3)
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#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
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#define CFG_SYS_TMRINTR_NO (INT_TMR3)
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#define CFG_SYS_TMRINTR_MASK (INT_ISR_INT24)
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#define CFG_SYS_TMRINTR_PEND (0)
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#define CFG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#endif /* CONFIG_M5272 */
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#ifdef CONFIG_M5275
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#include <asm/immap_5275.h>
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#include <asm/m5275.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (192)
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
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#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (0x1E)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#endif /* CONFIG_M5275 */
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#ifdef CONFIG_M5282
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#include <asm/immap_5282.h>
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#include <asm/m5282.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR3)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
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#define CFG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
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#define CFG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#endif /* CONFIG_M5282 */
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#ifdef CONFIG_M5307
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#include <asm/immap_5307.h>
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#include <asm/m5307.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + \
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(CFG_SYS_UART_PORT * 0x40))
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#define CFG_SYS_INTR_BASE (MMAP_INTC)
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#define CFG_SYS_NUM_IRQS (64)
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (((volatile intctrl_t *) \
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(CFG_SYS_INTR_BASE))->ipr)
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#define CFG_SYS_TMRINTR_NO (31)
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#define CFG_SYS_TMRINTR_MASK (0x00000400)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \
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MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#endif /* CONFIG_M5307 */
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#if defined(CONFIG_MCF5301x)
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#include <asm/immap_5301x.h>
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#include <asm/m5301x.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
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#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (6)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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#endif /* CONFIG_M5301x */
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#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
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#include <asm/immap_5329.h>
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#include <asm/m5329.h>
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
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#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (6)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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#endif /* CONFIG_M5329 && CONFIG_M5373 */
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#if defined(CONFIG_M54418)
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#include <asm/immap_5441x.h>
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#include <asm/m5441x.h>
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#if (CFG_SYS_UART_PORT < 4)
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#define CFG_SYS_UART_BASE (MMAP_UART0 + \
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(CFG_SYS_UART_PORT * 0x4000))
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#else
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#define CFG_SYS_UART_BASE (MMAP_UART4 + \
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((CFG_SYS_UART_PORT - 4) * 0x4000))
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#endif
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#define MMAP_DSPI MMAP_DSPI0
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/* Timer */
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#if CONFIG_IS_ENABLED(MCFTMR)
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#define CFG_SYS_UDELAY_BASE (MMAP_DTMR0)
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#define CFG_SYS_TMR_BASE (MMAP_DTMR1)
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#define CFG_SYS_TMRPND_REG (((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
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#define CFG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (6)
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#define CFG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
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#else
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#define CFG_SYS_UDELAY_BASE (MMAP_PIT0)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (192)
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#endif /* CONFIG_M54418 */
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#ifdef CONFIG_M547x
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#include <asm/immap_547x_8x.h>
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#include <asm/m547x_8x.h>
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#ifdef CONFIG_FSLDMAFEC
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#define FEC0_RX_TASK 0
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#define FEC0_TX_TASK 1
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#define FEC0_RX_PRIORITY 6
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#define FEC0_TX_PRIORITY 7
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#define FEC0_RX_INIT 16
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#define FEC0_TX_INIT 17
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#define FEC1_RX_TASK 2
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#define FEC1_TX_TASK 3
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#define FEC1_RX_PRIORITY 6
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#define FEC1_TX_PRIORITY 7
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#define FEC1_RX_INIT 30
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#define FEC1_TX_INIT 31
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#endif
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#define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
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#ifdef CONFIG_SLTTMR
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#define CFG_SYS_UDELAY_BASE (MMAP_SLT1)
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#define CFG_SYS_TMR_BASE (MMAP_SLT0)
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#define CFG_SYS_TMRPND_REG (((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
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#define CFG_SYS_TMRINTR_NO (INT0_HI_SLT0)
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#define CFG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
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#define CFG_SYS_TMRINTR_PEND (CFG_SYS_TMRINTR_MASK)
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#define CFG_SYS_TMRINTR_PRI (0x1E)
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#define CFG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
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#endif
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#define CFG_SYS_INTR_BASE (MMAP_INTC0)
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#define CFG_SYS_NUM_IRQS (128)
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#ifdef CONFIG_PCI
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#define CFG_SYS_PCI_BAR0 (0x40000000)
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#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE)
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#define CFG_SYS_PCI_TBATR0 (CFG_SYS_MBAR)
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#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE)
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#endif
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#endif /* CONFIG_M547x */
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#endif /* __IMMAP_H */
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