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https://github.com/AsahiLinux/u-boot
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dd4fdc0b14
This patch adds support for MediaTek MT7620 SoC. All files are dedicated for u-boot. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
103 lines
2.6 KiB
C
103 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MT7620_H_
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#define _MT7620_H_
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#include <linux/bitops.h>
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#define SYSCTL_BASE 0x10000000
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#define SYSCTL_SIZE 0x100
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#define MEMCTL_BASE 0x10000300
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#define MEMCTL_SIZE 0x100
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#define UARTFULL_BASE 0x10000500
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#define UARTFULL_SIZE 0x100
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#define UARTLITE_BASE 0x10000c00
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#define UARTLITE_SIZE 0x100
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#define SYSCTL_CHIP_REV_ID_REG 0x0c
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#define PKG_ID BIT(16)
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#define PKG_ID_A 1
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#define PKG_ID_N 0
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#define VER_S 8
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#define VER_M GENMASK(11, 8)
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#define ECO_S 0
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#define ECO_M GENMASK(3, 0)
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#define SYSCTL_SYSCFG0_REG 0x10
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#define XTAL_FREQ_SEL BIT(6)
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#define XTAL_40MHZ 1
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#define XTAL_20MHZ 0
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#define DRAM_TYPE_S 4
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#define DRAM_TYPE_M GENMASK(5, 4)
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#define DRAM_SDRAM 3
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#define DRAM_DDR2 2
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#define DRAM_DDR1 1
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#define DRAM_SDRAM_E1 0
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#define CHIP_MODE_S 0
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#define CHIP_MODE_M GENMASK(3, 0)
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#define SYSCTL_SYSCFG1_REG 0x14
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#define GE2_MODE_S 14
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#define GE2_MODE_M GENMASK(15, 14)
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#define GE1_MODE_S 12
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#define GE1_MODE_M GENMASK(13, 12)
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#define USB0_HOST_MODE BIT(10)
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#define PCIE_RC_MODE BIT(8)
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#define GE_MODE_M GENMASK(1, 0)
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#define SYSCTL_RSTCTL_REG 0x34
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#define MC_RST BIT(10)
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#define SYS_RST BIT(0)
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#define SYSCTL_CLKCFG0_REG 0x2c
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#define PERI_CLK_SEL BIT(4)
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#define SYSCTL_CPU_SYS_CLKCFG_REG 0x3c
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#define CPU_OCP_RATIO_S 16
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#define CPU_OCP_RATIO_M GENMASK(19, 16)
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#define CPU_FDIV_S 8
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#define CPU_FDIV_M GENMASK(12, 8)
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#define CPU_FFRAC_S 0
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#define CPU_FFRAC_M GENMASK(4, 0)
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#define SYSCTL_CUR_CLK_STS_REG 0x44
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#define CUR_CPU_OCP_RATIO_S 16
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#define CUR_CPU_OCP_RATIO_M GENMASK(19, 16)
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#define CUR_CPU_FDIV_S 8
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#define CUR_CPU_FDIV_M GENMASK(12, 8)
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#define CUR_CPU_FFRAC_S 0
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#define CUR_CPU_FFRAC_M GENMASK(4, 0)
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#define SYSCTL_CPLL_CFG0_REG 0x54
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#define CPLL_SW_CFG BIT(31)
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#define PLL_MULT_RATIO_S 16
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#define PLL_MULT_RATIO_M GENMASK(18, 16)
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#define PLL_DIV_RATIO_S 10
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#define PLL_DIV_RATIO_M GENMASK(11, 10)
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#define SSC_UP_BOUND_S 8
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#define SSC_UP_BOUND_M GENMASK(9, 8)
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#define SSC_EN BIT(7)
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#define SSC_SWING_S 4
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#define SSC_SWING_M GENMASK(6, 4)
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#define SYSCTL_CPLL_CFG1_REG 0x58
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#define CPLL_PD BIT(26)
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#define CPU_CLK_AUX1 BIT(25)
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#define CPU_CLK_AUX0 BIT(24)
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#define CPLL_LD BIT(23)
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#define SYSCTL_GPIOMODE_REG 0x60
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#define UARTL_GPIO_MODE BIT(5)
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#define UARTF_SHARE_MODE_S 2
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#define UARTF_SHARE_MODE_M GENMASK(4, 2)
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#define UARTF_MODE_UARTF_GPIO 5
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void mt7620_dram_init(void);
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void mt7620_get_clks(u32 *cpu_clk, u32 *sys_clk, u32 *xtal_clk);
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#endif /* _MT7620_H_ */
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