mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
277 lines
8.1 KiB
C
277 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (c) 2015 Paul Thacker <paul.thacker@microchip.com>
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*
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*/
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#include <common.h>
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#include <wait_bit.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <mach/pic32.h>
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#include <mach/ddr.h>
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#include "ddr2_regs.h"
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#include "ddr2_timing.h"
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/* init DDR2 Phy */
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void ddr2_phy_init(void)
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{
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struct ddr2_phy_regs *ddr2_phy;
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u32 pad_ctl;
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ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
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/* PHY_DLL_RECALIB */
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writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) |
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RECALIB_CNT(0x10), &ddr2_phy->dll_recalib);
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/* PHY_PAD_CTRL */
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pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) |
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ODT_PULLDOWN(2) | ODT_PULLUP(3) |
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EXTRA_OEN_CLK(0) | NOEXT_DLL |
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DLR_DFT_WRCMD | HALF_RATE |
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DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) |
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RCVR_EN | PREAMBLE_DLY(2);
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writel(pad_ctl, &ddr2_phy->pad_ctrl);
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/* SCL_CONFIG_0 */
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writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) |
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SCL_ODTCSWW, &ddr2_phy->scl_config_1);
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/* SCL_CONFIG_1 */
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writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2);
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/* SCL_LAT */
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writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency);
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}
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/* start phy self calibration logic */
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static int ddr2_phy_calib_start(void)
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{
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struct ddr2_phy_regs *ddr2_phy;
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ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
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/* DDR Phy SCL Start */
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writel(SCL_START | SCL_EN, &ddr2_phy->scl_start);
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/* Wait for SCL for data byte to pass */
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return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS,
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true, CONFIG_SYS_HZ, false);
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}
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/* DDR2 Controller initialization */
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/* Target Agent Arbiter */
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static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl,
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const struct ddr2_arbiter_params *const param)
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{
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int i;
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for (i = 0; i < NUM_AGENTS; i++) {
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/* set min burst size */
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writel(i * MIN_LIM_WIDTH, &ctrl->tsel);
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writel(param->min_limit, &ctrl->minlim);
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/* set request period (4 * req_period clocks) */
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writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel);
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writel(param->req_period, &ctrl->reqprd);
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/* set number of burst accepted */
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writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel);
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writel(param->min_cmd_acpt, &ctrl->mincmd);
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}
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}
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const struct ddr2_arbiter_params *__weak board_get_ddr_arbiter_params(void)
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{
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/* default arbiter parameters */
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static const struct ddr2_arbiter_params arb_params[] = {
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{ .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x04,},
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{ .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,},
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{ .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,},
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{ .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,},
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{ .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,},
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};
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return &arb_params[0];
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}
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static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx,
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u32 hostcmd2, u32 hostcmd1, u32 delay)
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{
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u32 hc_delay;
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hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2;
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writel(hostcmd1, &ctrl->cmd10[cmd_idx]);
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writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]);
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}
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/* init DDR2 Controller */
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void ddr2_ctrl_init(void)
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{
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u32 wr2prech, rd2prech, wr2rd, wr2rd_cs;
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u32 ras2ras, ras2cas, prech2ras, temp;
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const struct ddr2_arbiter_params *arb_params;
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struct ddr2_ctrl_regs *ctrl;
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ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl));
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/* PIC32 DDR2 controller always work in HALF_RATE */
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writel(HALF_RATE_MODE, &ctrl->memwidth);
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/* Set arbiter configuration per target */
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arb_params = board_get_ddr_arbiter_params();
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ddr_set_arbiter(ctrl, arb_params);
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/* Address Configuration, model {CS, ROW, BA, COL} */
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writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) |
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(COL_HI_RSHFT << 24) | (SB_PRI << 29) |
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(EN_AUTO_PRECH << 30)), &ctrl->memcfg0);
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writel(ROW_ADDR_MASK, &ctrl->memcfg1);
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writel(COL_HI_MASK, &ctrl->memcfg2);
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writel(COL_LO_MASK, &ctrl->memcfg3);
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writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4);
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/* Refresh Config */
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writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) |
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REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) |
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MAX_PEND_REF(7),
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&ctrl->refcfg);
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/* Power Config */
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writel(ECC_EN(0) | ERR_CORR_EN(0) | EN_AUTO_PWR_DN(0) |
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EN_AUTO_SELF_REF(3) | PWR_DN_DLY(8) |
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SELF_REF_DLY(17) | PRECH_PWR_DN_ONLY(0),
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&ctrl->pwrcfg);
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/* Delay Config */
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wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL),
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DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL;
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wr2rd_cs = max_t(u32, wr2rd - 1, 3);
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wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL;
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rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL),
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DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2;
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ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL),
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DIV_ROUND_UP(T_RRD_TCK, 2)) - 1;
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ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1;
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prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1;
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writel(((wr2rd & 0x0f) |
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((wr2rd_cs & 0x0f) << 4) |
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((BL - 1) << 8) |
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(BL << 12) |
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((BL - 1) << 16) |
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((BL - 1) << 20) |
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((BL + 2) << 24) |
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((RL - WL + 3) << 28)), &ctrl->dlycfg0);
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writel(((T_CKE_TCK - 1) |
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(((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) |
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((T_CKE_TCK - 1) << 16) |
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((max_t(u32, T_XP_TCK, T_CKE_TCK) - 1) << 20) |
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((wr2prech >> 4) << 26) |
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((wr2rd >> 4) << 27) |
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((wr2rd_cs >> 4) << 28) |
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(((RL + 5) >> 4) << 29) |
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((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1);
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writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) |
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(rd2prech << 8) |
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((wr2prech & 0x0f) << 12) |
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(ras2ras << 16) |
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(ras2cas << 20) |
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(prech2ras << 24) |
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((RL + 3) << 28)), &ctrl->dlycfg2);
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writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) |
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((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) |
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((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)),
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&ctrl->dlycfg3);
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/* ODT Config */
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writel(0x0, &ctrl->odtcfg);
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writel(BIT(16), &ctrl->odtencfg);
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writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3),
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&ctrl->odtcfg);
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/* Transfer Configuration */
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writel(NXTDATRQDLY(2) | NXDATAVDLY(4) | RDATENDLY(2) |
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MAX_BURST(3) | (7 << 28) | BIG_ENDIAN(0),
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&ctrl->xfercfg);
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/* DRAM Initialization */
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/* CKE high after reset and wait 400 nsec */
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host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000);
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/* issue precharge all command */
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host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK);
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/* initialize EMR2 */
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host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK * T_CK);
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/* initialize EMR3 */
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host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK * T_CK);
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/*
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* RDQS disable, DQSB enable, OCD exit, 150 ohm termination,
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* AL=0, DLL enable
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*/
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host_load_cmd(ctrl, 4, 0x100,
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LOAD_MODE_CMD | (0x40 << 24), T_MRD_TCK * T_CK);
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/*
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* PD fast exit, WR REC = T_WR in clocks -1,
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* DLL reset, CAS = RL, burst = 4
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*/
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temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1;
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host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24),
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T_MRD_TCK * T_CK);
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/* issue precharge all command */
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host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK);
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/* issue refresh command */
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host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN);
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/* issue refresh command */
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host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN);
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/* Mode register programming as before without DLL reset */
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host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24),
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T_MRD_TCK * T_CK);
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/* extended mode register same as before with OCD default */
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host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24),
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T_MRD_TCK * T_CK);
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/* extended mode register same as before with OCD exit */
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host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28),
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140 * T_CK);
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writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue);
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/* start memory initialization */
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writel(INIT_START, &ctrl->memcon);
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/* wait for all host cmds to be transmitted */
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wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false,
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CONFIG_SYS_HZ, false);
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/* inform all cmds issued, ready for normal operation */
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writel(INIT_START | INIT_DONE, &ctrl->memcon);
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/* perform phy caliberation */
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if (ddr2_phy_calib_start())
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printf("ddr2: phy calib failed\n");
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}
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phys_size_t ddr2_calculate_size(void)
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{
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u32 temp;
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temp = 1 << (COL_BITS + BA_BITS + ROW_BITS);
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/* 16-bit data width between controller and DIMM */
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temp = temp * CS_BITS * (16 / 8);
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return (phys_size_t)temp;
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}
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