mirror of
https://github.com/AsahiLinux/u-boot
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080fe39b8c
This isn't strictly needed as these firewalls should all be disabled on GP, but it also doesn't hurt, so do this unconditionally to remove this use of CONFIG_TI_SECURE_DEVICE. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
407 lines
11 KiB
C
407 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* AM6: SoC specific initialization
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*
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* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <spl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sysfw-loader.h>
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#include <asm/arch/sys_proto.h>
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#include "common.h"
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#include <dm.h>
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#include <dm/uclass-internal.h>
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#include <dm/pinctrl.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include <log.h>
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#include <mmc.h>
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#include <stdlib.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_K3_LOAD_SYSFW
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struct fwl_data main_cbass_fwls[] = {
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{ "MMCSD1_CFG", 2057, 1 },
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{ "MMCSD0_CFG", 2058, 1 },
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{ "USB3SS0_SLV0", 2176, 2 },
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{ "PCIE0_SLV", 2336, 8 },
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{ "PCIE1_SLV", 2337, 8 },
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{ "PCIE0_CFG", 2688, 1 },
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{ "PCIE1_CFG", 2689, 1 },
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}, mcu_cbass_fwls[] = {
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{ "MCU_ARMSS0_CORE0_SLV", 1024, 1 },
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{ "MCU_ARMSS0_CORE1_SLV", 1028, 1 },
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{ "MCU_FSS0_S1", 1033, 8 },
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{ "MCU_FSS0_S0", 1036, 8 },
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{ "MCU_CPSW0", 1220, 1 },
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};
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#endif
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static void ctrl_mmr_unlock(void)
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{
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/* Unlock all WKUP_CTRL_MMR0 module registers */
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
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mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
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/* Unlock all MCU_CTRL_MMR0 module registers */
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mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
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mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
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/* Unlock all CTRL_MMR0 module registers */
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mmr_unlock(CTRL_MMR0_BASE, 0);
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mmr_unlock(CTRL_MMR0_BASE, 1);
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mmr_unlock(CTRL_MMR0_BASE, 2);
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mmr_unlock(CTRL_MMR0_BASE, 3);
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mmr_unlock(CTRL_MMR0_BASE, 6);
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mmr_unlock(CTRL_MMR0_BASE, 7);
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}
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/*
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* This uninitialized global variable would normal end up in the .bss section,
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* but the .bss is cleared between writing and reading this variable, so move
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* it to the .data section.
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*/
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u32 bootindex __section(".data");
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static void store_boot_index_from_rom(void)
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{
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bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
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}
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#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
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void k3_mmc_stop_clock(void)
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{
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if (spl_boot_device() == BOOT_DEVICE_MMC1) {
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struct mmc *mmc = find_mmc_device(0);
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if (!mmc)
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return;
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mmc->saved_clock = mmc->clock;
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mmc_set_clock(mmc, 0, true);
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}
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}
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void k3_mmc_restart_clock(void)
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{
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if (spl_boot_device() == BOOT_DEVICE_MMC1) {
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struct mmc *mmc = find_mmc_device(0);
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if (!mmc)
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return;
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mmc_set_clock(mmc, mmc->saved_clock, false);
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}
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}
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#else
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void k3_mmc_stop_clock(void) {}
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void k3_mmc_restart_clock(void) {}
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#endif
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#if CONFIG_IS_ENABLED(DFU) || CONFIG_IS_ENABLED(USB_STORAGE)
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#define CTRLMMR_SERDES0_CTRL 0x00104080
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#define PCIE_LANE0 0x1
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static int fixup_usb_boot(void)
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{
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int ret;
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switch (spl_boot_device()) {
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case BOOT_DEVICE_USB:
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/*
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* If bootmode is Host bootmode, fixup the dr_mode to host
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* before the dwc3 bind takes place
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*/
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ret = fdt_find_and_setprop((void *)gd->fdt_blob,
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"/bus@100000/dwc3@4000000/usb@10000",
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"dr_mode", "host", 5, 0);
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if (ret)
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printf("%s: fdt_find_and_setprop() failed:%d\n", __func__,
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ret);
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fallthrough;
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case BOOT_DEVICE_DFU:
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/*
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* The serdes mux between PCIe and USB3 needs to be set to PCIe for
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* accessing the interface at USB 2.0
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*/
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writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
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default:
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break;
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}
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return 0;
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}
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int fdtdec_board_setup(const void *fdt_blob)
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{
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return fixup_usb_boot();
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}
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#endif
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static void setup_am654_navss_northbridge(void)
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{
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/*
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* NB0 is bridge to SRAM and NB1 is bridge to DDR.
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* To ensure that SRAM transfers are not stalled due to
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* delays during DDR refreshes, SRAM traffic should be higher
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* priority (threadmap=2) than DDR traffic (threadmap=0).
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*/
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writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP);
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writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP);
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}
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void board_init_f(ulong dummy)
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{
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#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
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struct udevice *dev;
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size_t pool_size;
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void *pool_addr;
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int ret;
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#endif
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/*
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* Cannot delay this further as there is a chance that
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* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
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*/
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store_boot_index_from_rom();
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/* Make all control module registers accessible */
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ctrl_mmr_unlock();
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setup_am654_navss_northbridge();
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#ifdef CONFIG_CPU_V7R
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disable_linefill_optimization();
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setup_k3_mpu_regions();
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#endif
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/* Init DM early in-order to invoke system controller */
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spl_early_init();
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#ifdef CONFIG_K3_EARLY_CONS
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/*
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* Allow establishing an early console as required for example when
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* doing a UART-based boot. Note that this console may not "survive"
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* through a SYSFW PM-init step and will need a re-init in some way
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* due to changing module clock frequencies.
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*/
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early_console_init();
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#endif
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#ifdef CONFIG_K3_LOAD_SYSFW
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/*
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* Initialize an early full malloc environment. Do so by allocating a
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* new malloc area inside the currently active pre-relocation "first"
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* malloc pool of which we use all that's left.
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*/
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pool_size = CONFIG_VAL(SYS_MALLOC_F_LEN) - gd->malloc_ptr;
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pool_addr = malloc(pool_size);
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if (!pool_addr)
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panic("ERROR: Can't allocate full malloc pool!\n");
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mem_malloc_init((ulong)pool_addr, (ulong)pool_size);
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gd->flags |= GD_FLG_FULL_MALLOC_INIT;
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debug("%s: initialized an early full malloc pool at 0x%08lx of 0x%lx bytes\n",
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__func__, (unsigned long)pool_addr, (unsigned long)pool_size);
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/*
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* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
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* regardless of the result of pinctrl. Do this without probing the
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* device, but instead by searching the device that would request the
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* given sequence number if probed. The UART will be used by the system
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* firmware (SYSFW) image for various purposes and SYSFW depends on us
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* to initialize its pin settings.
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*/
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ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
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if (!ret)
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pinctrl_select_state(dev, "default");
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/*
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* Load, start up, and configure system controller firmware while
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* also populating the SYSFW post-PM configuration callback hook.
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*/
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k3_sysfw_loader(false, k3_mmc_stop_clock, k3_mmc_restart_clock);
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/* Prepare console output */
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preloader_console_init();
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/* Disable ROM configured firewalls right after loading sysfw */
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remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
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remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
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#else
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/* Prepare console output */
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preloader_console_init();
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#endif
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/* Output System Firmware version info */
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k3_sysfw_print_ver();
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/* Perform EEPROM-based board detection */
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if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
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do_board_detect();
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#if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
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ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
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&dev);
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if (ret)
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printf("AVS init failed: %d\n", ret);
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#endif
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#ifdef CONFIG_K3_AM654_DDRSS
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret)
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panic("DRAM init failed: %d\n", ret);
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#endif
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spl_enable_dcache();
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}
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u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
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{
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#if defined(CONFIG_SUPPORT_EMMC_BOOT)
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
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/* eMMC boot0 mode is only supported for primary boot */
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if (bootindex == K3_PRIMARY_BOOTMODE &&
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bootmode == BOOT_DEVICE_MMC1)
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return MMCSD_MODE_EMMCBOOT;
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#endif
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/* Everything else use filesystem if available */
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#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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static u32 __get_backup_bootmedia(u32 devstat)
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{
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u32 bkup_boot = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
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switch (bkup_boot) {
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case BACKUP_BOOT_DEVICE_USB:
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return BOOT_DEVICE_USB;
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case BACKUP_BOOT_DEVICE_UART:
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return BOOT_DEVICE_UART;
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case BACKUP_BOOT_DEVICE_ETHERNET:
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return BOOT_DEVICE_ETHERNET;
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case BACKUP_BOOT_DEVICE_MMC2:
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{
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u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
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if (port == 0x0)
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return BOOT_DEVICE_MMC1;
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return BOOT_DEVICE_MMC2;
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}
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case BACKUP_BOOT_DEVICE_SPI:
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return BOOT_DEVICE_SPI;
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case BACKUP_BOOT_DEVICE_HYPERFLASH:
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return BOOT_DEVICE_HYPERFLASH;
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case BACKUP_BOOT_DEVICE_I2C:
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return BOOT_DEVICE_I2C;
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};
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return BOOT_DEVICE_RAM;
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}
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static u32 __get_primary_bootmedia(u32 devstat)
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{
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u32 bootmode = (devstat & CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT;
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if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
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bootmode = BOOT_DEVICE_SPI;
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if (bootmode == BOOT_DEVICE_MMC2) {
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u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_MMC_PORT_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_MMC_PORT_SHIFT;
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if (port == 0x0)
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bootmode = BOOT_DEVICE_MMC1;
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} else if (bootmode == BOOT_DEVICE_MMC1) {
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u32 port = (devstat & CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_EMMC_PORT_SHIFT;
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if (port == 0x1)
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bootmode = BOOT_DEVICE_MMC2;
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} else if (bootmode == BOOT_DEVICE_DFU) {
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u32 mode = (devstat & CTRLMMR_MAIN_DEVSTAT_USB_MODE_MASK) >>
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CTRLMMR_MAIN_DEVSTAT_USB_MODE_SHIFT;
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if (mode == 0x2)
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bootmode = BOOT_DEVICE_USB;
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}
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return bootmode;
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}
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u32 spl_boot_device(void)
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{
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u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
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if (bootindex == K3_PRIMARY_BOOTMODE)
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return __get_primary_bootmedia(devstat);
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else
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return __get_backup_bootmedia(devstat);
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}
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#ifdef CONFIG_SYS_K3_SPL_ATF
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#define AM6_DEV_MCU_RTI0 134
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#define AM6_DEV_MCU_RTI1 135
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#define AM6_DEV_MCU_ARMSS0_CPU0 159
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#define AM6_DEV_MCU_ARMSS0_CPU1 245
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void release_resources_for_core_shutdown(void)
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{
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
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struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
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int ret;
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u32 i;
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const u32 put_device_ids[] = {
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AM6_DEV_MCU_RTI0,
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AM6_DEV_MCU_RTI1,
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};
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/* Iterate through list of devices to put (shutdown) */
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for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
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u32 id = put_device_ids[i];
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ret = dev_ops->put_device(ti_sci, id);
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if (ret)
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panic("Failed to put device %u (%d)\n", id, ret);
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}
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const u32 put_core_ids[] = {
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AM6_DEV_MCU_ARMSS0_CPU1,
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AM6_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
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};
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/* Iterate through list of cores to put (shutdown) */
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for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
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u32 id = put_core_ids[i];
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/*
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* Queue up the core shutdown request. Note that this call
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* needs to be followed up by an actual invocation of an WFE
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* or WFI CPU instruction.
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*/
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ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
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if (ret)
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panic("Failed sending core %u shutdown message (%d)\n",
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id, ret);
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}
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}
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#endif
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