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79642098a8
This patch add support for the Network Space v2 board and parents, based on the Marvell Kirkwood 6281 SoC. This include Network Space (Max) v2 and Internet Space v2. Additional information is available at: http://lacie-nas.org/doku.php?id=network_space_v2 Signed-off-by: Simon Guinot <sguinot@lacie.com>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
/*
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* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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*
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* Based on Kirkwood support:
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <command.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include <asm/arch/gpio.h>
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#include "netspace_v2.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/* Gpio configuration */
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kw_config_gpio(NETSPACE_V2_OE_VAL_LOW, NETSPACE_V2_OE_VAL_HIGH,
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NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_SPI_SCn,
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MPP1_SPI_MOSI,
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MPP2_SPI_SCK,
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MPP3_SPI_MISO,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO, /* Fan speed (bit 1) */
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO, /* Red led */
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MPP14_GPIO, /* USB fuse */
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MPP16_GPIO, /* SATA 0 power */
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MPP17_GPIO, /* SATA 1 power */
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP22_GPIO, /* Fan speed (bit 0) */
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MPP23_GPIO, /* Fan power */
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MPP24_GPIO, /* USB mode select */
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MPP25_GPIO, /* Fan rotation fail */
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MPP26_GPIO, /* USB vbus-in detection */
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MPP28_GPIO, /* USB enable vbus-out */
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MPP29_GPIO, /* Blue led (slow register) */
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MPP30_GPIO, /* Blue led (command register) */
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MPP31_GPIO, /* Board power off */
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MPP32_GPIO, /* Button (0 = Released, 1 = Pushed) */
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MPP33_GPIO, /* Fan speed (bit 2) */
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0
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};
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kirkwood_mpp_conf(kwmpp_config);
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return 0;
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}
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int board_init(void)
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{
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/* Machine number */
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
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/* Boot parameters address */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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return 0;
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}
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void mv_phy_88e1116_init(char *name)
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{
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u16 reg;
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u16 devadr;
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if (miiphy_set_current_dev(name))
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return;
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/* command to read PHY dev address */
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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printf("Err..(%s) could not read PHY dev address\n", __func__);
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return;
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}
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/*
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* Enable RGMII delay on Tx and Rx for CPU port
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* Ref: sec 4.7.2 of chip datasheet
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*/
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
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/* reset the phy */
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if (miiphy_read(name, devadr, MII_BMCR, ®) != 0) {
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printf("Err..(%s) PHY status read failed\n", __func__);
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return;
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}
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if (miiphy_write(name, devadr, MII_BMCR, reg | 0x8000) != 0) {
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printf("Err..(%s) PHY reset failed\n", __func__);
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return;
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}
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debug("88E1116 Initialized on %s\n", name);
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}
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/* Configure and initialize PHY */
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void reset_phy(void)
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{
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mv_phy_88e1116_init("egiga0");
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}
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/* Return GPIO button status */
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static int
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do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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return kw_gpio_get_value(NETSPACE_V2_GPIO_BUTTON);
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}
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U_BOOT_CMD(button, 1, 1, do_read_button,
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"Return GPIO button status 0=off 1=on", "");
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