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5c214bac46
All zynqmp boards have been already described via mdio node that's why also convert the rest of the boards. With using mdio node there is an option to add reset property for the whole mdio bus which is reflected by 's/phy-reset-gpios/reset-gpios/g' for some boards. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
457 lines
7.5 KiB
Text
457 lines
7.5 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP zc1751-xm019-dc5
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*
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* (C) Copyright 2015 - 2021, Xilinx, Inc.
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*
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* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/ {
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model = "ZynqMP zc1751-xm019-dc5 RevA";
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compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem1 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem1_default>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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&gpio {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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pinctrl-1 = <&pinctrl_i2c0_gpio>;
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scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_i2c0_default: i2c0-default {
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mux {
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groups = "i2c0_18_grp";
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function = "i2c0";
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};
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conf {
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groups = "i2c0_18_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c0_gpio: i2c0-gpio {
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mux {
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groups = "gpio0_74_grp", "gpio0_75_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_74_grp", "gpio0_75_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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mux {
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groups = "i2c1_19_grp";
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function = "i2c1";
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};
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conf {
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groups = "i2c1_19_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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mux {
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groups = "gpio0_76_grp", "gpio0_77_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_76_grp", "gpio0_77_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_uart0_default: uart0-default {
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mux {
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groups = "uart0_17_grp";
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function = "uart0";
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};
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conf {
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groups = "uart0_17_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO70";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO71";
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bias-disable;
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};
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};
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pinctrl_uart1_default: uart1-default {
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mux {
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groups = "uart1_18_grp";
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function = "uart1";
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};
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conf {
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groups = "uart1_18_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO73";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO72";
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bias-disable;
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};
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};
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pinctrl_gem1_default: gem1-default {
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mux {
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function = "ethernet1";
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groups = "ethernet1_0_grp";
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};
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conf {
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groups = "ethernet1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
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"MIO49";
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bias-high-impedance;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
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"MIO43";
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bias-disable;
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low-power-enable;
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};
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mux-mdio {
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function = "mdio1";
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groups = "mdio1_0_grp";
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};
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conf-mdio {
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groups = "mdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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};
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pinctrl_sdhci0_default: sdhci0-default {
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mux {
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groups = "sdio0_0_grp";
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function = "sdio0";
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};
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conf {
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groups = "sdio0_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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mux-cd {
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groups = "sdio0_cd_0_grp";
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function = "sdio0_cd";
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};
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conf-cd {
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groups = "sdio0_cd_0_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux-wp {
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groups = "sdio0_wp_0_grp";
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function = "sdio0_wp";
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};
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conf-wp {
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groups = "sdio0_wp_0_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_watchdog0_default: watchdog0-default {
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mux-clk {
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groups = "swdt0_clk_1_grp";
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function = "swdt0_clk";
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};
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conf-clk {
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groups = "swdt0_clk_1_grp";
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bias-pull-up;
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};
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mux-rst {
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groups = "swdt0_rst_1_grp";
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function = "swdt0_rst";
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};
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conf-rst {
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groups = "swdt0_rst_1_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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};
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pinctrl_ttc0_default: ttc0-default {
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mux-clk {
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groups = "ttc0_clk_0_grp";
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function = "ttc0_clk";
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};
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conf-clk {
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groups = "ttc0_clk_0_grp";
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bias-pull-up;
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};
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mux-wav {
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groups = "ttc0_wav_0_grp";
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function = "ttc0_wav";
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};
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conf-wav {
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groups = "ttc0_wav_0_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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};
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pinctrl_ttc1_default: ttc1-default {
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mux-clk {
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groups = "ttc1_clk_0_grp";
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function = "ttc1_clk";
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};
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conf-clk {
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groups = "ttc1_clk_0_grp";
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bias-pull-up;
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};
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mux-wav {
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groups = "ttc1_wav_0_grp";
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function = "ttc1_wav";
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};
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conf-wav {
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groups = "ttc1_wav_0_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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};
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pinctrl_ttc2_default: ttc2-default {
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mux-clk {
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groups = "ttc2_clk_0_grp";
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function = "ttc2_clk";
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};
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conf-clk {
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groups = "ttc2_clk_0_grp";
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bias-pull-up;
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};
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mux-wav {
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groups = "ttc2_wav_0_grp";
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function = "ttc2_wav";
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};
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conf-wav {
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groups = "ttc2_wav_0_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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};
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pinctrl_ttc3_default: ttc3-default {
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mux-clk {
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groups = "ttc3_clk_0_grp";
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function = "ttc3_clk";
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};
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conf-clk {
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groups = "ttc3_clk_0_grp";
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bias-pull-up;
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};
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mux-wav {
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groups = "ttc3_wav_0_grp";
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function = "ttc3_wav";
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};
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conf-wav {
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groups = "ttc3_wav_0_grp";
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bias-disable;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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};
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};
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&sdhci0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci0_default>;
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no-1-8-v;
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xlnx,mio-bank = <0>;
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};
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&ttc0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ttc0_default>;
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};
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&ttc1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ttc1_default>;
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};
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&ttc2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ttc2_default>;
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};
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&ttc3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ttc3_default>;
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};
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&uart0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0_default>;
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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&watchdog0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_watchdog0_default>;
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};
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