mirror of
https://github.com/AsahiLinux/u-boot
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53677ef18e
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
441 lines
17 KiB
C
441 lines
17 KiB
C
/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2005-2007
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* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_405EP 1 /* this is a PPC405 CPU */
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#define CONFIG_4xx 1 /* member of PPC4xx family */
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#define CONFIG_TAIHU 1 /* on a taihu board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_NO_SERIAL_EEPROM
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/*----------------------------------------------------------------------------*/
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#ifdef CONFIG_NO_SERIAL_EEPROM
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/*
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!-------------------------------------------------------------------------------
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! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
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! assuming a 33MHz input clock to the 405EP from the C9531.
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!-------------------------------------------------------------------------------
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*/
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#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_3)
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#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
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#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
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PLL_MALDIV_1 | PLL_PCIDIV_1)
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#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
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#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
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#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
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#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
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#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
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#endif
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/*----------------------------------------------------------------------------*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootfile=/tftpboot/taihu/uImage\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"netdev=eth0\0" \
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"hostname=taihu\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"kernel_addr=FC000000\0" \
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"ramdisk_addr=FC180000\0" \
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"load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \
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"update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \
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"cp.b 200000 FFFC0000 40000\0" \
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"upd=run load update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0x14 /* PHY address */
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
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#define CONFIG_NET_MULTI 1
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#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_PHY_RESET 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_SPI
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
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#define CFG_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
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#define CFG_SDRAM_BANKS 2
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch])
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*/
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
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/* SDRAM timings used in datasheet */
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#define CFG_SDRAM_CL 3 /* CAS latency */
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#define CFG_SDRAM_tRP 20 /* PRECHARGE command period */
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#define CFG_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
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#define CFG_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
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#define CFG_SDRAM_tRFC 66 /* Auto refresh period */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/*
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* If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
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* If CFG_405_UART_ERRATA_59, then UART divisor is 31.
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* Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
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* The Linux BASE_BAUD define should match this configuration.
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* baseBaud = cpuClock/(uartDivisor*16)
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* If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
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* set Linux BASE_BAUD to 403200.
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*/
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
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#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
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#define CFG_BASE_BAUD 691200
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_UART1_CONSOLE 1
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/* The following table includes the supported baudrates */
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_LOOPW 1 /* enable loopw command */
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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/*-----------------------------------------------------------------------
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* I2C stuff
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
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#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
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#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
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#define CONFIG_SOFT_SPI
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#define SPI_SCL spi_scl
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#define SPI_SDA spi_sda
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#define SPI_READ spi_read()
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#define SPI_DELAY udelay(2)
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#ifndef __ASSEMBLY__
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void spi_scl(int);
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void spi_sda(int);
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unsigned char spi_read(void);
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#endif
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/* standard dtt sensor configuration */
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#define CONFIG_DTT_DS1775 1
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#define CONFIG_DTT_SENSORS { 0 }
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#define CFG_I2C_DTT_ADDR 0x49
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* resource configuration */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
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#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
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#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
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#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
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#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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#define CONFIG_EEPRO100 1
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFE00000
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_ADDR0 0x555
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#define CFG_FLASH_ADDR1 0x2aa
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#define CFG_FLASH_WORD_SIZE unsigned short
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
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#define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
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#ifdef CFG_ENV_IS_IN_NVRAM
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#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
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#define CFG_ENV_ADDR \
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(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env*/
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#endif
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/*-----------------------------------------------------------------------
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* PPC405 GPIO Configuration
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*/
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#define CFG_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
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{ \
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/* GPIO Core 0 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
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{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
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} \
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}
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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/* use on chip memory (OCM) for temperary stack until sdram is tested */
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#define CFG_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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#define CFG_OCM_DATA_ADDR 0xF8000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* External Bus Controller (EBC) Setup
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|
*/
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|
|
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/* Memory Bank 0 (Flash/SRAM) initialization */
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#define CFG_EBC_PB0AP 0x03815600
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#define CFG_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
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/* Memory Bank 1 (NVRAM/RTC) initialization */
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#define CFG_EBC_PB1AP 0x05815600
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#define CFG_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
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/* Memory Bank 2 (USB device) initialization */
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#define CFG_EBC_PB2AP 0x03016600
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#define CFG_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
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|
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/* Memory Bank 3 (LCM and D-flip-flop) initialization */
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|
#define CFG_EBC_PB3AP 0x158FF600
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#define CFG_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
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|
|
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/* Memory Bank 4 (not install) initialization */
|
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#define CFG_EBC_PB4AP 0x158FF600
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#define CFG_EBC_PB4CR 0x5021A000
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|
|
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#define CPLD_REG0_ADDR 0x50100000
|
|
#define CPLD_REG1_ADDR 0x50100001
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
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|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/* pass open firmware flat tree */
|
|
#define CONFIG_OF_LIBFDT 1
|
|
#define CONFIG_OF_BOARD_SETUP 1
|
|
|
|
#endif /* __CONFIG_H */
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