mirror of
https://github.com/AsahiLinux/u-boot
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323d1f9d5b
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
104 lines
2 KiB
C
104 lines
2 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <mach/init.h>
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#include <mach/sg-regs.h>
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int memconf_init(const struct uniphier_board_data *bd)
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{
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u32 tmp = 0;
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unsigned long size_per_word;
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tmp = readl(SG_MEMCONF);
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tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
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switch (bd->dram_ch0_width) {
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case 16:
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tmp |= SG_MEMCONF_CH0_NUM_1;
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size_per_word = bd->dram_ch0_size;
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break;
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case 32:
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tmp |= SG_MEMCONF_CH0_NUM_2;
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size_per_word = bd->dram_ch0_size >> 1;
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break;
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default:
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pr_err("error: unsupported DRAM Ch0 width\n");
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return -EINVAL;
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}
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/* Set DDR size */
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switch (size_per_word) {
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case SZ_64M:
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tmp |= SG_MEMCONF_CH0_SZ_64M;
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break;
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case SZ_128M:
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tmp |= SG_MEMCONF_CH0_SZ_128M;
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break;
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case SZ_256M:
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tmp |= SG_MEMCONF_CH0_SZ_256M;
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break;
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case SZ_512M:
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tmp |= SG_MEMCONF_CH0_SZ_512M;
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break;
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case SZ_1G:
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tmp |= SG_MEMCONF_CH0_SZ_1G;
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break;
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default:
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pr_err("error: unsupported DRAM Ch0 size\n");
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return -EINVAL;
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}
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tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
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switch (bd->dram_ch1_width) {
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case 16:
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tmp |= SG_MEMCONF_CH1_NUM_1;
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size_per_word = bd->dram_ch1_size;
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break;
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case 32:
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tmp |= SG_MEMCONF_CH1_NUM_2;
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size_per_word = bd->dram_ch1_size >> 1;
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break;
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default:
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pr_err("error: unsupported DRAM Ch1 width\n");
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return -EINVAL;
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}
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switch (size_per_word) {
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case SZ_64M:
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tmp |= SG_MEMCONF_CH1_SZ_64M;
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break;
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case SZ_128M:
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tmp |= SG_MEMCONF_CH1_SZ_128M;
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break;
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case SZ_256M:
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tmp |= SG_MEMCONF_CH1_SZ_256M;
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break;
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case SZ_512M:
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tmp |= SG_MEMCONF_CH1_SZ_512M;
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break;
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case SZ_1G:
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tmp |= SG_MEMCONF_CH1_SZ_1G;
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break;
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default:
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pr_err("error: unsupported DRAM Ch1 size\n");
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return -EINVAL;
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}
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if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
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tmp |= SG_MEMCONF_SPARSEMEM;
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else
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tmp &= ~SG_MEMCONF_SPARSEMEM;
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writel(tmp, SG_MEMCONF);
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return 0;
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}
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