mirror of
https://github.com/AsahiLinux/u-boot
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e162c6b1a7
Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Simon Glass <sjg@chromium.org>
177 lines
4 KiB
C
177 lines
4 KiB
C
/*
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* Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
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* Copyright (C) 2015 Toradex AG
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*
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* Based on ehci-mx6 driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <usb.h>
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#include <errno.h>
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#include <linux/compiler.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/imx-common/regs-usbphy.h>
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#include <usb/ehci-ci.h>
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#include "ehci.h"
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#define USB_NC_REG_OFFSET 0x00000800
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#define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6)
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#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
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#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
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/* USBCMD */
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#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
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#define UCMD_RESET (1 << 1) /* controller reset */
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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USB_PHY1_BASE_ADDR,
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};
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static const unsigned nc_reg_bases[] = {
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USBC0_BASE_ADDR,
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USBC1_BASE_ADDR,
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};
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static void usb_internal_phy_clock_gate(int index)
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{
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void __iomem *phy_reg;
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phy_reg = (void __iomem *)phy_bases[index];
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clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE);
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}
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static void usb_power_config(int index)
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{
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struct anadig_reg __iomem *anadig =
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(struct anadig_reg __iomem *)ANADIG_BASE_ADDR;
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void __iomem *pll_ctrl;
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switch (index) {
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case 0:
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pll_ctrl = &anadig->pll3_ctrl;
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clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
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setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
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| ANADIG_PLL3_CTRL_POWERDOWN
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| ANADIG_PLL_CTRL_EN_USB_CLKS);
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break;
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case 1:
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pll_ctrl = &anadig->pll7_ctrl;
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clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
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setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
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| ANADIG_PLL7_CTRL_POWERDOWN
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| ANADIG_PLL_CTRL_EN_USB_CLKS);
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break;
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default:
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return;
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}
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}
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static void usb_phy_enable(int index, struct usb_ehci *ehci)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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void __iomem *usb_cmd;
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phy_reg = (void __iomem *)phy_bases[index];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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usb_cmd = (void __iomem *)&ehci->usbcmd;
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/* Stop then Reset */
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clrbits_le32(usb_cmd, UCMD_RUN_STOP);
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while (readl(usb_cmd) & UCMD_RUN_STOP)
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;
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setbits_le32(usb_cmd, UCMD_RESET);
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while (readl(usb_cmd) & UCMD_RESET)
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;
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/* Reset USBPHY module */
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setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Remove CLKGATE and SFTRST */
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clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Power up the PHY */
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writel(0, phy_reg + USBPHY_PWD);
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/* Enable FS/LS device */
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setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
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USBPHY_CTRL_ENUTMILEVEL3);
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}
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static void usb_oc_config(int index)
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{
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void __iomem *ctrl;
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ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET);
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setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
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}
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int __weak board_usb_phy_mode(int port)
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{
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return 0;
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}
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci;
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enum usb_init_type type;
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if (index >= ARRAY_SIZE(nc_reg_bases))
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return -EINVAL;
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ehci = (struct usb_ehci *)nc_reg_bases[index];
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/* Do board specific initialisation */
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board_ehci_hcd_init(index);
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usb_power_config(index);
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usb_oc_config(index);
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usb_internal_phy_clock_gate(index);
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usb_phy_enable(index, ehci);
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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type = board_usb_phy_mode(index);
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if (type != init)
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return -ENODEV;
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if (init == USB_INIT_DEVICE) {
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setbits_le32(&ehci->usbmode, CM_DEVICE);
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writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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} else if (init == USB_INIT_HOST) {
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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}
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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